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US-12622027-B2 - Silicon carbide wafer and silicon carbide semiconductor device including the same

US12622027B2US 12622027 B2US12622027 B2US 12622027B2US-12622027-B2

Abstract

A silicon carbide wafer includes: a substrate made of silicon carbide; and an epitaxial layer made of silicon carbide and arranged on the substrate. A chip formation region is defined in which a semiconductor element is formed, and an outer peripheral region is defined to surround the chip formation region. The epitaxial layer has a trap density of 1.0×10 13 cm −3 or less at an activation energy of 0.10 to 0.20 eV derived by a DLTS method in the chip formation region. The substrate has a Ti density of 1.0×10 17 cm −3 or less measured by a SIMS method and a Cr density of 1.0×10 17 cm −3 or less measured by a SIMS method.

Inventors

  • Hideyuki Uehigashi

Assignees

  • DENSO CORPORATION
  • TOYOTA JIDOSHA KABUSHIKI KAISHA
  • MIRISE Technologies Corporation

Dates

Publication Date
20260505
Application Date
20231113
Priority Date
20221226

Claims (6)

  1. 1 . A silicon carbide wafer made of silicon carbide comprising: a substrate made of silicon carbide; and an epitaxial layer made of silicon carbide and arranged on the substrate, wherein a chip formation region is defined in which a semiconductor element is formed, and an outer peripheral region is defined to surround the chip formation region, the epitaxial layer has a trap density of 1.0×10 13 cm −3 or less at an activation energy of 0.10 to 0.20 eV derived by a DLTS method in the chip formation region, and the substrate has a Ti density of 1.0×10 17 cm −3 or less measured by a SIMS method and a Cr density of 1.0×10 17 cm −3 or less measured by a SIMS method.
  2. 2 . The silicon carbide wafer according to claim 1 , wherein the epitaxial layer has a deviation in a carrier concentration distribution along a plane direction of the substrate, and the deviation is within 15%.
  3. 3 . The silicon carbide wafer according to claim 1 , wherein a part of the epitaxial layer has an impurity concentration of 5.0×10 13 to 1.0×10 19 cm −3 .
  4. 4 . The silicon carbide wafer according to claim 1 , wherein the epitaxial layer has a thickness of 4 to 300 μm.
  5. 5 . The silicon carbide wafer according to claim 1 , wherein the epitaxial layer includes a buffer layer located adjacent to the substrate and a drift layer located on the buffer layer, and the buffer layer has an impurity concentration of 1.0×10 16 to 1.0×10 19 cm −3 .
  6. 6 . A silicon carbide semiconductor device comprising: the silicon carbide wafer according to claim 1 ; and a semiconductor element in which a current flows along a stacking direction of the substrate and the epitaxial layer.

Description

CROSS REFERENCE TO RELATED APPLICATION This application is based on Japanese Patent Application No. 2022-208927 filed on Dec. 26, 2022, the disclosure of which is incorporated herein by reference. TECHNICAL FIELD The present disclosure relates to a silicon carbide wafer made of silicon carbide and a silicon carbide semiconductor device using the silicon carbide wafer. BACKGROUND A silicon carbide (SiC) semiconductor device includes a semiconductor element such as a MOSFET formed using a SiC wafer. The SiC wafer is formed by growing an epitaxial layer of SiC on a substrate formed of SiC. SUMMARY According to an aspect of the present disclosure, a silicon carbide wafer includes: a substrate made of silicon carbide; and an epitaxial layer made of silicon carbide and arranged on the substrate. A chip formation region is defined in which a semiconductor element is formed, and an outer peripheral region is defined to surround the chip formation region. The epitaxial layer has a trap density of 1.0×1013 cm−3 or less at an activation energy of 0.10 to 0.20 eV derived by a DLTS method in the chip formation region. The substrate has a Ti density of 1.0×1017 cm−3 or less measured by a SIMS method and a Cr density of 1.0×1017 cm−3 or less measured by a SIMS method. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of a SiC semiconductor device according to an embodiment. FIG. 2 is a graph showing a relationship between a temperature and a signal obtained by a DLTS method. FIG. 3 is a plan view of a SiC wafer. FIG. 4 is a graph showing a relationship between a Ti density in a substrate measured by a SIMS method and a Ti trap density in an epitaxial layer obtained by a DLTS method. DETAILED DESCRIPTION Conventionally, there has been proposed a silicon carbide (SiC) semiconductor device in which a SiC wafer is used to form a semiconductor element such as a MOSFET. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor. The SiC wafer is formed by growing an epitaxial layer of SiC on a substrate formed of SiC. For example, the SiC semiconductor device in which the MOSFET is formed has the following configuration. The MOSFET includes an n-type substrate, an n-type drift layer disposed on the substrate, a p-type base layer disposed on the drift layer, and an n-type source region formed in a surface layer portion of the base layer. The MOSFET includes a trench gate structure formed to penetrate the source region and reach the drift layer, a first electrode electrically connected to the base layer and the source region, and a second electrode connected to the substrate. Such a SiC semiconductor device is configured as follows. A SiC wafer is formed by disposing an n-type epitaxial layer on a wafer-like substrate. Then, ion implantation or the like is performed to form a base layer, a source region, and the like. The SiC wafer is divided into chips. Note that the drift layer is constituted by a portion of the epitaxial layer that is different from a portion constituting the base layer or the source region. The SiC semiconductor device is expected to replace the existing semiconductor device formed of silicon over a wide voltage range, specifically, an application range of 100 V to 10 kV or more. In this case, in order to obtain an ultrahigh breakdown voltage device in which the breakdown voltage of the SiC semiconductor device exceeds 10 kV, an epitaxial layer having a low concentration (i.e., the drift layer) is required in order to obtain a conductivity modulation effect. For example, the impurity concentration of the epitaxial layer may be 1.0×1014 cm−3 or less in order to obtain an ultra-high breakdown voltage device. The present inventor conducts intensive studies on the establishment of a technique for producing an epitaxial layer (that is, the drift layer) applicable to all of the above-described voltage range. Specifically, the inventor intensively studies a technique for intentionally controlling the impurity concentration of the epitaxial layer. Then, the present inventor focuses on the fact that it is necessary to reduce the influence of the trap density in the epitaxial layer in order to make the impurity concentration of the epitaxial layer 1.0×1014 cm−3 or less. It is known that Ti (titanium) or Cr (chromium) acts as n-type impurities by forming a level at a position shallow from a conduction band when being taken into an epitaxial layer, such that the breakdown voltage of the SiC semiconductor device is affected. In order to make the trap density of the epitaxial layer less likely to affect the breakdown voltage, the trap density of the epitaxial layer is preferably about 10% lower than the impurity concentration of the epitaxial layer. That is, in order to set the impurity concentration of the epitaxial layer to 1.0×1014 cm−3 or less, the trap density of the epitaxial layer is preferably set to 1.0×1013 cm−3 or less. In case of a device having a lower breakdown voltage, f