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US-12622028-B2 - SiC semiconductor device, and manufacturing method therefor

US12622028B2US 12622028 B2US12622028 B2US 12622028B2US-12622028-B2

Abstract

A method for manufacturing an SiC semiconductor device includes a step of setting, on a main surface of an SiC wafer, a scheduled cutting line that demarcates a plurality of chip regions including a first chip region in which a functional device is formed and a second chip region in which a monitor pattern for performing process control of the first chip region is formed, a step of forming, on the main surface, a plurality of main surface electrodes respectively covering the chip regions such as to expose the scheduled cutting line and respectively forming a portion of the functional device and a portion of the monitor pattern, a step of irradiating laser light to the scheduled cutting line and forming a modified region, and a step of cleaving the SiC wafer with the modified region as a starting point.

Inventors

  • Shingo Ota

Assignees

  • ROHM CO., LTD.

Dates

Publication Date
20260505
Application Date
20200616
Priority Date
20190617

Claims (20)

  1. 1 . A method for manufacturing an SiC semiconductor device comprising: a step of preparing an SiC wafer having a main surface and constituted of an SiC monocrystal; a step of setting, on the main surface, a scheduled cutting line that demarcates chip regions including a first chip region in which a functional device is to be formed and a second chip region as a dummy chip region in which a monitor pattern for performing process control of the first chip region is to be formed; a step of forming, on the main surface, main surface electrodes respectively covering the chip regions such as to expose the scheduled cutting line and respectively forming a portion of the functional device and a portion of the monitor pattern; a step of irradiating laser light to the scheduled cutting line exposed from the main surface electrodes and forming a modified region that is modified to be of a property differing from the SiC monocrystal; and a step of cutting out the SiC semiconductor device from the first chip region and a dummy SiC semiconductor device from the second chip region by cleaving the SiC wafer with the modified region as a starting point; wherein the step of setting the scheduled cutting line includes a step of forming, on the main surface in the first and second chip regions, alignment patterns each formed of a material other than a metal material and indicating the scheduled cutting line.
  2. 2 . The method for manufacturing the SiC semiconductor device according to claim 1 , further comprising: a step of forming, on the main surface, insulating layers partially covering the main surface electrodes respectively and demarcating a dicing street that exposes the scheduled cutting line in a region between the chip regions that are mutually adjacent, prior to the step of forming the modified region; and wherein the laser light is irradiated to the scheduled cutting line exposed from the dicing street.
  3. 3 . The method for manufacturing the SiC semiconductor device according to claim 2 , wherein the insulating layers each having an inclined surface that demarcates the dicing street are formed.
  4. 4 . The method for manufacturing the SiC semiconductor device according to claim 3 , wherein the insulating layers each have the inclined surface that is recessed in curved shape.
  5. 5 . The method for manufacturing the SiC semiconductor device according to claim 2 , wherein the dicing street has a width of not less than 10% and not more than 50% of a thickness of the SiC wafer.
  6. 6 . The method for manufacturing the SiC semiconductor device according to claim 2 , wherein the insulating layers each include a resin layer.
  7. 7 . The method for manufacturing the SiC semiconductor device according to claim 2 , wherein the dicing street exposes entire regions of the alignment patterns in plan view.
  8. 8 . The method for manufacturing the SiC semiconductor device according to claim 1 , further comprising: a step of forming an interlayer insulating layer on the main surface after the step of setting the scheduled cutting line and prior to the step of forming the main surface electrode; and wherein the main surface electrode is formed on the interlayer insulating layer.
  9. 9 . The method for manufacturing the SiC semiconductor device according to claim 8 , wherein the interlayer insulating layer that covers the scheduled cutting line is formed, the laser light is irradiated to the SiC wafer via the interlayer insulating layer, and the SiC wafer is cleaved together with the interlayer insulating layer.
  10. 10 . The method for manufacturing the SiC semiconductor device according to claim 1 , wherein the scheduled cutting line of lattice shape that extends in an a-axis direction and an m-axis direction of the SiC monocrystal and demarcates the chip regions in a matrix aligned in the a-axis direction and the m-axis direction of the SiC monocrystal is set, and the SiC wafer is cleaved in the a-axis direction and the m-axis direction of the SiC monocrystal.
  11. 11 . The method for manufacturing the SiC semiconductor device according to claim 10 , wherein the second chip regions opposing each other in the a-axis direction of the SiC monocrystal across one or the first chip regions are included.
  12. 12 . The method for manufacturing the SiC semiconductor device according to claim 10 , wherein the second chip regions opposing each other in the m-axis direction of the SiC monocrystal across one or the first chip regions are included.
  13. 13 . The method for manufacturing the SiC semiconductor device according to claim 1 , wherein the chip regions each have a peripheral edge portion, the alignment patterns are arranged in the peripheral edge portions of the chip regions, and the SiC wafer is cleaved such that the alignment patterns remain in the chip regions.
  14. 14 . The method for manufacturing the SiC semiconductor device according to claim 1 , wherein the scheduled cutting line of lattice shape that demarcates the chip regions in a matrix is set.
  15. 15 . The method for manufacturing the SiC semiconductor device according to claim 1 , wherein the number of the first chip regions is not less than 100 regions and not more than 10000 regions, and the number of the second chip regions is not less than 1 region and not more than 20 regions.
  16. 16 . The method for manufacturing the SiC semiconductor device according to claim 1 , wherein the first chip regions do not have a monitor pattern.
  17. 17 . The method for manufacturing the SiC semiconductor device according to claim 1 , wherein the SiC wafer that includes an SiC substrate and an SiC epitaxial layer and has the main surface constituted of the SiC epitaxial layer is prepared.
  18. 18 . An SiC semiconductor device comprising: an SiC chip having a first main surface and a side surface constituted of a cleavage surface; a modified region formed in the side surface and modified to be of a property differing from an SiC monocrystal; an alignment pattern as an accessory pattern formed in a peripheral edge portion of the main surface at an interval from the side surface; a main surface electrode formed on the first main surface at an interval from the alignment pattern; and an insulating layer formed on the first main surface at an interval from the side surface so as to cover the main surface electrode and expose an entire region of the alignment pattern in plan view; wherein the alignment pattern is formed of a material other than a metal material.
  19. 19 . The SiC semiconductor device according to claim 18 , wherein the alignment pattern includes a trench formed in the first main surface.
  20. 20 . The SiC semiconductor device according to claim 19 , wherein the alignment pattern includes an insulator embedded in the trench.

Description

TECHNICAL FIELD The present invention relates to an SiC semiconductor device and a method for manufacturing the same. BACKGROUND ART A method for manufacturing an SiC semiconductor device using a laser irradiation cleaving method has come to be noted in recent years. With the laser irradiation cleaving method, laser light is irradiated to an SiC wafer and the SiC wafer is cleaved along the portion irradiated by the laser light thereafter. With this method, the SiC wafer can be cut easily and therefore, manufacturing time can be shortened. On the other hand, with a method for manufacturing an SiC semiconductor device, a monitor pattern called a PCM (process control monitor) is formed in an arbitrary region of an SiC wafer. By the monitor pattern, a suitability of each step performed on the SiC wafer can be evaluated indirectly based on physical characteristics and electrical characteristics of the monitor pattern. The physical characteristics are, for example, dimensions of a structure formed in the monitor pattern. The electrical characteristics are, for example, a resistance value and a capacitance value of a semiconductor region, etc., formed in the monitor pattern. Patent Literature 1 discloses a method for manufacturing an SiC semiconductor device using an SiC wafer including accessory patterns (monitor patterns) that are concentratedly arranged at positions overlapping laser irradiation regions (scheduled cutting lines). CITATION LIST Patent Literature Patent Literature 1: Japanese Patent Application Publication No. 2016-134427 SUMMARY OF INVENTION Technical Problem With the SiC wafer according to Patent Literature 1, laser light is blocked by the monitor patterns and thus, unmodified portions in which modified regions are not present are formed in regions hidden by the monitor patterns. In a step of cleaving the SiC wafer, a force that maintains anatomic arrangement (a crystal structure of SiC) acts at the unmodified portions directly below the monitor patterns. Consequently, meanderings with the monitor patterns as starting points are formed in cleaved portions of the SiC wafer. A preferred embodiment of the present invention provides a method for manufacturing an SiC semiconductor device with which shape defects due to a monitor pattern can be suppressed. A preferred embodiment of the present invention provides an SiC semiconductor device having a structure with which shape defects due to an accessory pattern are suppressed. Solution to Problem A preferred embodiment of the present invention provides a method for manufacturing an SiC semiconductor device including a step of preparing an SiC wafer having a main surface and constituted of an SiC monocrystal, a step of setting, on the main surface, a scheduled cutting line that demarcates a plurality of chip regions including a first chip region in which a functional device is formed and a second chip region in which a monitor pattern for performing process control of the first chip region is formed, a step of forming, on the main surface, a plurality of main surface electrodes respectively covering the chip regions such as to expose the scheduled cutting line and respectively forming a portion of the functional device and a portion of the monitor pattern, a step of irradiating laser light to the scheduled cutting line exposed from the main surface electrodes and forming a modified region that is modified to be of a property differing from the SiC monocrystal, and a step of cleaving the SiC wafer with the modified region as a starting point. According to this method for manufacturing the SiC semiconductor device, shape defects due to the monitor pattern can be suppressed. Also, according to this method for manufacturing the SiC semiconductor device, an SiC semiconductor device having a structure with which shape defects due to the monitor pattern are suppressed can be manufactured and provided. A preferred embodiment of the present invention provides an SiC semiconductor device including an SiC chip having a first main surface and a second main surface respectively formed in quadrilateral shapes in plan view and four side surfaces respectively connecting the first main surface and the second main surface and respectively constituted of cleavage surfaces, a modified region formed in the respective side surfaces and modified to be of a property differing from an SiC monocrystal, an alignment pattern as an accessory pattern formed in a peripheral edge portion of the first main surface at intervals inward from the respective side surfaces in plan view, a main surface electrode formed on the first main surface at intervals inward from the respective side surfaces and exposing the alignment pattern in plan view, and an insulating layer formed on the first main surface at intervals inward from the respective side surfaces, partially covering the main surface electrode, and demarcating a dicing street that, with the side surfaces, exposes the alignment pattern