US-12622030-B2 - Silicon carbide semiconductor device

US12622030B2US 12622030 B2US12622030 B2US 12622030B2US-12622030-B2

Abstract

A silicon carbide semiconductor device includes a silicon carbide substrate that has first and second main surfaces and that includes a drift region being of a first-conductivity-type, a body region provided on the drift region and being of a second-conductivity-type, a source region provided on the body region and being of the first-conductivity-type, and a first electric field relaxation region being of the second-conductivity-type and including a first plane in which an impurity-concentration of the second-conductivity-type is a maximum and a second plane in which the impurity-concentration of the second-conductivity-type of 1/10 of the maximum, the second plane being closer to the second main surface than the first plane is. A distance between the first and second planes is 1.0 μm or greater, and a distance from the first main surface to an interface between the first electric field relaxation region and the drift region is 2.0 μm or greater.

Inventors

Yu Saitoh
Takeyoshi Masuda

Assignees

SUMITOMO ELECTRIC INDUSTRIES, LTD.

Dates

Publication Date: 20260505
Application Date: 20220531
Priority Date: 20210623

Claims (8)

1 . A silicon carbide semiconductor device comprising a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, wherein the silicon carbide substrate includes: a drift region being of a first conductivity type; a body region provided on the drift region, the body region being of a second conductivity type different from the first conductivity type; and a source region provided on the body region so as to be separated from the drift region, the source region being of the first conductivity type, wherein a gate trench is provided on the first main surface, the gate trench being defined by side surfaces passing through the source region and the body region to reach the drift region and a bottom surface continuous with the side surfaces, wherein the silicon carbide substrate further includes a first electric field relaxation region provided between the bottom surface and the second main surface, the first electric field relaxation region being of the second conductivity type, wherein the first electric field relaxation region includes, in a direction perpendicular to the first main surface, a first plane in which a concentration of an impurity of the second conductivity type is a maximum value, and a second plane in which a concentration of the impurity of the second conductivity type is 1/10 of the maximum value, the second plane being closer to the second main surface than the first plane is, wherein a distance between the first plane and the second plane is 1.0 μm or greater, and wherein a distance from the first main surface to an interface that is between the first electric field relaxation region and the drift region is 2.0 μm or greater.
2 . The silicon carbide semiconductor device according to claim 1 , wherein the first electric field relaxation region further contains an impurity of the first conductivity type, and wherein a total amount of the impurity of the second conductivity type contained in the first electric field relaxation region is greater than a total amount of the impurity of the first conductivity type contained in the first electric field relaxation region.
3 . The silicon carbide semiconductor device according to claim 1 , wherein a distance between the first main surface and the bottom surface is less than 0.8 μm, and wherein a distance between the first main surface and the first plane is 0.8 μm or greater.
4 . The silicon carbide semiconductor device according to claim 1 , wherein a maximum value of an effective concentration of the impurity of the second conductivity type in the body region is 1.0×10 18 cm −3 or greater and 5.0×10 18 cm −3 or less.
5 . The silicon carbide semiconductor device according to claim 1 , wherein the distance between the first main surface and the first plane is 3.0 μm or less.
6 . The silicon carbide semiconductor device according to claim 1 , wherein the silicon carbide semiconductor device has an active region including the body region, the source region, and the first electric field relaxation region, and has a termination region provided around the active region and including a second electric field relaxation region being of the second conductivity type, wherein the second electric field relaxation region includes, in the direction perpendicular to the first main surface, a third plane in which a concentration of the impurity of the second conductivity type is a maximum value, and a fourth plane in which a concentration of the impurity of the second conductivity type is 1/10 of the maximum value, the fourth plane being closer to the second main surface than the third plane is, and wherein a distance between the third plane and the fourth plane is 1.0 μm or greater.
7 . The silicon carbide semiconductor device according to claim 6 , wherein the second electric field relaxation region is electrically connected to the first electric field relaxation region.
8 . The silicon carbide semiconductor device according to claim 1 , wherein the side surfaces of the gate trench include a {0-33-8} plane.

Description

TECHNICAL FIELD The present disclosure relates to a silicon carbide semiconductor device. This application claims priority to Japanese Patent Application No. 2021-104166 filed on Jun. 23, 2021, the entire contents of which are incorporated herein by reference. BACKGROUND ART As one of the silicon carbide semiconductor devices, a metal oxide semiconductor field effect transistor (MOSFET) including a gate trench passing through a source region and a body region is disclosed (for example, Patent Document 1). CITATION LIST Patent Document [Patent Document 1] Japanese Laid-open Patent Application Publication No. 2014-41990 SUMMARY OF THE INVENTION A silicon carbide semiconductor device includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface. The silicon carbide substrate includes a drift region being of a first conductivity type; a body region provided on the drift region, the body region being of a second conductivity type different from the first conductivity type; and a source region provided on the body region so as to be separated from the drift region, the source region being of the first conductivity type. A gate trench is provided on the first main surface. The gate trench is defined by side surfaces passing through the source region and the body region to reach the drift region and a bottom surface continuous with the side surfaces. The silicon carbide substrate further includes a first electric field relaxation region provided between the bottom surface and the second main surface, the first electric field relaxation region being of the second conductivity type. The first electric field relaxation region includes, in a direction perpendicular to the first main surface, a first plane in which a concentration of an impurity of the second conductivity type is a maximum value, and a second plane, in which a concentration of the impurity of the second conductivity type is 1/10 of the maximum value, and the second plane is closer to the second main surface than the first plane is. A distance between the first plane and the second plane is 1.0 μm or greater, and a distance from the first main surface to an interface that is between the first electric field relaxation region and the drift region is 2.0 μm or greater. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a drawing illustrating a layout of a silicon carbide semiconductor device according to an embodiment. FIG. 2 is a cross-sectional view illustrating a configuration of the silicon carbide semiconductor device according to the embodiment. FIG. 3 is a graph illustrating an example of a concentration profile of a p-type impurity in an electric field relaxation region in the embodiment. FIG. 4 is a cross-sectional view (part 1) illustrating a method for manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 5 is a cross-sectional view (part 2) illustrating the method for manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 6 is a cross-sectional view (part 3) illustrating the method for manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 7 is a cross-sectional view (part 4) illustrating the method for manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 8 is a cross-sectional view (part 5) illustrating the method for manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 9 is a cross-sectional view (part 6) illustrating the method for manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 10 is a cross-sectional view (part 7) illustrating the method for manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 11 is a cross-sectional view (part 8) illustrating the method for manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 12 is a cross-sectional view (part 9) illustrating the method for manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 13 is a graph illustrating examples of a concentration profile of a p-type impurity in an electric field relaxation region in the reference example and the embodiment. FIG. 14 is a graph illustrating a relationship between a drain voltage and a drain current in the embodiment and the reference example. FIG. 15 is a cross-sectional view illustrating a configuration of a silicon carbide semiconductor device according to a modified example of the embodiment. EMBODIMENT FOR CARRYING OUT THE INVENTION Problems to be Solved by the Present Disclosure In order to manufacture a conventional silicon carbide semiconductor device, it is necessary to form an epitaxial layer on a silicon carbide single-crystal substrate multiple times. In order to reduce the cost, it is desired to reduce the number of times of forming the epitaxial layer. It is an object of