US-12622031-B2 - Method of manufacturing a semiconductor device and a semiconductor device

US12622031B2US 12622031 B2US12622031 B2US 12622031B2US-12622031-B2

Abstract

In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked over a bottom fin structure protruding from a substrate, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer is formed on an end of each of the etched first semiconductor layers. One or more epitaxial layers are formed in the source/drain space, and the sacrificial gate structure is replaced with a metal gate structure. A width of the source/drain space at a bottommost one of the first semiconductor layers is greater than a width of the source/drain space at one of the first semiconductor layers above the bottommost one of the first semiconductor layers.

Inventors

Jhon Jhy Liaw

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date: 20260505
Application Date: 20220422

Claims (20)

1 . A method of manufacturing a semiconductor device, comprising: forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked over a bottom fin structure protruding from a substrate, the fin structure extending lengthwise along a first direction; forming a sacrificial gate structure over the fin structure, the sacrificial gate structure extending lengthwise along a second direction perpendicular to the first direction; forming gate sidewall spacers along sidewall of the sacrificial gate structure; etching a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a source/drain space; laterally etching the first semiconductor layers through the source/drain space; forming an inner spacer made of a dielectric material on an end of each of the etched first semiconductor layers; forming one or more epitaxial layers in the source/drain space; removing a sacrificial gate electrode and a sacrificial gate dielectric layer included in the sacrificial gate structure, thereby forming a gate space; removing parts of the first semiconductor layers in the gate space, thereby leaving channel regions constituted by the second semiconductor layers; forming a gate dielectric layer to wrap around each of the second semiconductor layers in the gate space and to interface a top surface of the bottom fin structure; forming a gate electrode over the gate dielectric layer; after the forming of the gate electrode, forming a gate end dielectric layer to interface the gate electrode along the second direction; recessing the gate dielectric layer, the gate electrode and the gate sidewall spacers to form a gate recess; and depositing a cap dielectric layer over the gate recess, wherein a width of the source/drain space at a bottommost one of the first semiconductor layers is smaller than a width of the source/drain space at one of the first semiconductor layers above the bottommost one of the first semiconductor layers, wherein the forming of the gate electrode forms a bottom channel length G 2 with respect to the bottom fin structure and an upper channel length G 1 with respect to the second semiconductor layers, wherein the bottom channel length G 2 is greater than the upper channel length G 1 .
2 . The method of claim 1 , further comprising: after the forming of the one or more epitaxial layers in the source/drain space, depositing an etch stop layer over the one or more epitaxial layers, wherein, after the recessing, a top surface of the etch stop layer is higher than top surfaces of the gate sidewall spacers, wherein a bottom of the source/drain space has a tapered shape of which width decreases toward the substrate.
3 . The method of claim 1 , wherein G 2 /G 1 is in a range from 1.05 to 1.4.
4 . The method of claim 1 , wherein a part of the gate electrode disposed between a bottommost one of the second semiconductor layers and the top surface of the bottom fin structure has a tapered shape in a cross section.
5 . The method of claim 4 , wherein a bottom width of the tapered shape is 1.05 to 1.4 times a top width of the tapered shape.
6 . The method of claim 1 , wherein a planar channel region is formed at the bottom fin structure.
7 . The method of claim 1 , wherein the source/drain space penetrates the bottom fin structure by an amount of 5 nm to 35 nm.
8 . The method of claim 1 , wherein a thickness of a bottommost one of the first semiconductor layers is greater than a thickness of the first semiconductor layers other than the bottommost one of the first semiconductor layers.
9 . The method of claim 1 , wherein, in a top view, the gate end dielectric layer is disposed between the gate sidewall spacers along the first direction.
10 . A method of manufacturing a semiconductor device, comprising: forming a first fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked over a first bottom fin structure protruding from a substrate; forming a second fin structure in which third semiconductor layer and forth semiconductor layers are alternately stacked over a second bottom fin structure protruding from the substrate; forming a sacrificial gate structure over the first fin structure and the second fin structure; etching a first source/drain region of the first fin structure and a second source/drain region of the second fin structure, which are not covered by the sacrificial gate structure, thereby forming a first source/drain space over the first fin structure and a second source/drain space over the second fin structure; laterally etching the first semiconductor layers through the first source/drain space and the third semiconductor layers through the second source/drain space; forming a first inner spacer made of a dielectric material on an end of each of the etched first semiconductor layers and a second inner spacer made of the dielectric material on an end of each of the etched third semiconductor layers; forming one or more epitaxial layers in the first source/drain space and the second source/drain space; removing the sacrificial gate structure, thereby forming a gate space; removing parts of the first semiconductor layers and parts of the third semiconductor layers in the gate space, thereby leaving first channel regions constituted by the second semiconductor layers and second channel regions constituted by the fourth semiconductor layers; forming a gate dielectric layer to wrap around each of the second semiconductor layers and each of the fourth semiconductor layers in the gate space, the gate dielectric layer interfacing top surfaces of the first bottom fin structure and the second bottom fin structure; forming a first gate electrode over the gate dielectric layer above the second semiconductor layers and a second gate electrode over the gate dielectric layer above the fourth semiconductor layers, wherein a composition of the first gate electrode is different from a composition of the second gate electrode, wherein the first gate electrode interfaces the second gate electrode; and forming a gate contact on the first gate electrode, wherein the gate contact is closer to the second semiconductor layers than the fourth semiconductor layers, wherein a thickness of a bottommost one of the first semiconductor layers is greater than a thickness of the first semiconductor layers other than the bottommost one of the first semiconductor layers, wherein the forming of the first gate electrode forms a bottom channel length G 2 with respect to the first bottom fin structure and an upper channel length G 1 with respect to the first semiconductor layers, wherein the bottom channel length G 2 is greater than the upper channel length G 1 .
11 . The method of claim 10 , wherein G 2 /G 1 is in a range from 1.05 to 1.4.
12 . The method of claim 10 , wherein a part of the first gate electrode disposed between a bottommost one of the second semiconductor layers and the top surface of the first bottom fin structure has a tapered shape in a cross section.
13 . The method of claim 12 , wherein a bottom width of the tapered shape is 1.05 to 1.4 times a top width of the tapered shape.
14 . The method of claim 10 , further comprising: forming a first gate end dielectric layer adjacent the first gate electrode; forming a second gate end dielectric layer adjacent the second gate electrode; and recessing the first gate electrode and the second gate electrode such that top surfaces of the first gate end dielectric layer and the second gate end dielectric layer are higher than top surfaces of the first gate electrode and the second gate electrode, wherein a planar channel region is formed at the bottom fin structure.
15 . The method of claim 10 , wherein the first source/drain space penetrates the first bottom fin structure by an amount of 5 nm to 35 nm.
16 . The method of claim 10 , further comprising: forming a gate spacer along sidewalls of the sacrificial gate structure, wherein a dielectric constant of the first inner spacer is greater than a dielectric constant of the gate spacer.
17 . A method of manufacturing a semiconductor device, comprising: forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked over a bottom fin structure protruding from a substrate, the fin structure extending lengthwise along a first direction; forming a sacrificial gate structure over the fin structure, the sacrificial gate structure including a sacrificial gate electrode and a sacrificial gate dielectric layer and extending lengthwise along a second direction perpendicular to the first direction; forming gate sidewall spacers along sidewall of the sacrificial gate structure; etching a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a source/drain space; laterally etching the first semiconductor layers through the source/drain space; forming an inner spacer made of a dielectric material on an end of each of the etched first semiconductor layers; forming one or more epitaxial layers in the source/drain space; depositing an etch stop layer over the one or more epitaxial layers; forming an interlayer dielectric layer over the etch stop layer; removing the sacrificial gate electrode and the sacrificial gate dielectric layer, thereby forming a gate space; recessing the gate sidewall spacers; removing parts of the first semiconductor layers in the gate space, thereby leaving channel regions constituted by the second semiconductor layers; forming a gate dielectric layer to wrap around each of the second semiconductor layers in the gate space; forming a gate electrode over the gate dielectric layer, wherein: a planar channel region is formed at the bottom fin structure, and a channel length of the planar channel region is greater than a channel length of each of the channel regions constituted by the second semiconductor layers; after the forming of the gate electrode, forming a gate end dielectric layer to interface the gate electrode along the second direction, recessing the gate dielectric layer, the gate electrode and the gate sidewall spacers to form a gate recess; depositing a cap dielectric layer over the gate recess; and planarizing the cap dielectric layer such that top surfaces of the cap dielectric layer, the etch stop layer, and the interlayer dielectric layer are coplanar, wherein a dielectric constant of the inner spacer is greater than a dielectric constant of the gate sidewall spacers.
18 . The method of claim 17 , wherein a vertical length of the recessed gate sidewall spacer is greater than a vertical length of the inner spacer.
19 . The method of claim 17 , wherein a thickness S 2 of a bottommost one of the first semiconductor layers is greater than a thickness S 1 of the first semiconductor layers other than the bottommost one of the first semiconductor layers.
20 . The method of claim 19 , wherein S 2 /S 1 is in a range from 1.05 to 1.3.

Description

RELATED APPLICATION This application claims priority to U.S. Provisional Application No. 63/309,971 filed Feb. 14, 2022, the entire contents of which are incorporated herein by reference. BACKGROUND As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as a multi-gate field effect transistor (FET), including a fin FET (Fin FET) and a gate-all-around (GAA) FET. In a Fin FET, a gate electrode is adjacent to three side surfaces of a channel region with a gate dielectric layer interposed therebetween. Because the gate structure surrounds (wraps) the fin on three surfaces, the transistor essentially has three gates controlling the current through the fin or channel region. Unfortunately, the fourth side, the bottom part of the channel is far away from the gate electrode and thus is not under close gate control. In contrast, in a GAA FET, all side surfaces of the channel region are surrounded by the gate electrode, which allows for fuller depletion in the channel region and results in less short-channel effects due to steeper sub-threshold current swing (SS) and smaller drain induced barrier lowering (DIBL). As transistor dimensions are continually scaled down to sub 10-15 nm technology nodes, further improvements of the GAA FET are required. BRIEF DESCRIPTION OF THE DRAWINGS The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 shows a plan view (layout view) of a semiconductor device including one or more GAA FET devices according to an embodiment of the present disclosure. FIGS. 2A, 2B, 2C and 2D show various views of a GAA FET device according to an embodiment of the present disclosure. FIG. 2A is a cross sectional view along the X direction (source-to-drain direction) corresponding to line C1 of FIG. 1, FIG. 2B is a cross sectional view along the X direction corresponding to line C2 of FIG. 1, FIG. 2C is a cross sectional view along the Y direction corresponding to line C3 of FIG. 1 and FIG. 2D shows a cross sectional view along the Y direction corresponding to line C4 of FIG. 1. FIGS. 3A, 3B, 3C and 3D show various views of a GAA FET device according to an embodiment of the present disclosure. FIG. 3A is a cross sectional view along the X direction (source-to-drain direction) corresponding to line C1 of FIG. 1, FIG. 3B is a cross sectional view along the X direction corresponding to line C2 of FIG. 1, FIG. 3C is a cross sectional view along the Y direction corresponding to line C3 of 1 and FIG. 3D shows a cross sectional view along the Y direction corresponding to line C4 of FIG. 1. FIG. 4 shows one of the various stages of manufacturing a semiconductor GAA FET device according to an embodiment of the present disclosure. FIG. 5 shows one of the various stages of manufacturing a semiconductor GAA FET device according to an embodiment of the present disclosure. FIGS. 6A and 6B show one of the various stages of manufacturing a semiconductor GAA FET device according to an embodiment of the present disclosure. FIG. 7 shows one of the various stages of manufacturing a semiconductor GAA FET device according to an embodiment of the present disclosure. FIG. 8 shows one of the various stages of manufacturing a semiconductor GAA FET device according to an embodiment of the present disclosure. FIG. 9 shows one of the various stages of manufacturing a semiconductor GAA FET device according to an embodiment of the present disclosure. FIG. 10 shows one of the various stages of manufacturing a semiconductor GAA FET device according to an embodiment of the present disclosure. FIG. 11 shows one of the various stages of manufacturing a semiconductor GAA FET device according to an embodiment of the present disclosure. FIG. 12 shows one of the various stages of manufacturing a semiconductor GAA FET device according to an embodiment of the present disclosure. FIG. 13 shows one of the various stages of manufacturing a semiconductor GAA FET device according to an embodiment of the present disclosure. FIG. 14 shows one of the various stages of manufacturing a semiconductor GAA FET device according to an embodiment of the present disclosure. FIG. 15 shows one of the various stages of manufacturing a semiconductor GAA FET device according to an embodiment of the present disclosure. FIG. 16 shows one of the various stages of manufacturing a semiconductor GAA FET device according to an embodiment of the present disclosure. FIGS. 17A, 17B and 17C show one of the vari