US-12622032-B2 - Memory device having a floating gate with a nano-dot region and method for fabricating the same

Abstract

An embodiment memory device includes a drain electrode disposed on a semiconductor substrate, a channel region in contact with the drain electrode, a source electrode in contact with the channel region, and a floating gate region in contact with the source electrode and the drain electrode, the floating gate region including a nano-dot region including at least one nano-dot gate, wherein the drain electrode is overlapped with the nano-dot region, and wherein the nano-dot region is overlapped with the channel region.

Inventors

• Jong Seok Lee
• Tae Ho Jeong
• Ui Yeon WON
• Woo Jong YU

Assignees

• HYUNDAI MOTOR COMPANY
• KIA CORPORATION
• Research & Business Foundation Sungkyunkwan University

Dates

Publication Date

20260505

Application Date

20220725

Priority Date

20211008

Claims (20)

1. 1 . A memory device comprising: a drain electrode disposed on a semiconductor substrate; a channel region in contact with the drain electrode; a source electrode in contact with the channel region; and a floating gate region in contact with the source electrode and the drain electrode, the floating gate region comprising a nano-dot region comprising at least one nano-dot gate, wherein the drain electrode overlaps the nano-dot region, wherein the nano-dot region overlaps the channel region, and wherein the drain electrode comprises: a first electrode in contact with an upper surface of the semiconductor substrate and extending in parallel to the upper surface of the semiconductor substrate, a second electrode in contact with an upper surface of the first electrode and in contact with a lateral side of the floating gate region, and extending perpendicular to the upper surface of the semiconductor substrate, and a third electrode in contact with an upper surface of the second electrode and in contact and overlapping with an upper surface of the floating gate region, and extending in parallel to the upper surface of the semiconductor substrate.
2. 2 . The memory device of claim 1 , wherein an overlap region between the nano-dot region and the channel region is overlapped with the drain electrode.
3. 3 . The memory device of claim 1 , wherein the third electrode overlaps the nano-dot region and the channel region.
4. 4 . The memory device of claim 1 , wherein the channel region is interposed between the semiconductor substrate and the floating gate region.
5. 5 . The memory device of claim 1 , wherein the channel region comprises: a first region in contact with the drain electrode while extending in parallel to a first surface of the drain electrode; a second region in contact with the lateral side of the floating gate region while extending perpendicularly to the first surface of the drain electrode; and a third region in contact with a first surface of the floating gate region while extending in parallel to the first surface of the drain electrode.
6. 6 . The memory device of claim 5 , wherein the third region is overlapped with the nano-dot region and the drain electrode.
7. 7 . The memory device of claim 5 , wherein the drain electrode is interposed between the semiconductor substrate and the channel region.
8. 8 . The memory device of claim 1 , wherein the floating gate region includes an insulating layer region surrounding the at least one nano-dot gate.
9. 9 . The memory device of claim 8 , wherein the at least one nano-dot gate is electrically isolated from another nano-dot gate adjacent to the insulating layer region.
10. 10 . The memory device of claim 8 , wherein the insulating layer region comprises boron hexagonal nitride (h-BN), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), or silicon nitride.
11. 11 . The memory device of claim 1 , wherein the channel region comprises a semiconductor material.
12. 12 . The memory device of claim 11 , wherein the semiconductor material comprises zinc oxide (ZnO), molybdenum disulfide (MoS 2 ), tungsten diselenide (WSe 2 ), tungsten disulfide (WS 2 ), molybdenum diselenide (MoSe 2 ), silicon (Si), germanium (Ge), semiconductor carbon nano-tubes (CNT), or black phosphorus (BP).
13. 13 . The memory device of claim 11 , wherein the semiconductor material comprises zinc oxide (ZnO), molybdenum disulfide (MoS 2 ), tungsten diselenide (WSe 2 ), tungsten disulfide (WS 2 ), or molybdenum diselenide (MoSe 2 ).
14. 14 . The memory device of claim 1 , wherein the nano-dot gate comprises a metal material or graphene.
15. 15 . The memory device of claim 1 , wherein a distance from the drain electrode to the nano-dot gate is 10 nm or less.
16. 16 . A method of forming the memory device according to claim 1 , the method comprising: forming the drain electrode on the semiconductor substrate; forming the channel region in contact with the drain electrode; forming the source electrode in contact with the channel region; and forming the floating gate region in contact with the source electrode and the drain electrode, the floating gate region comprising the nano-dot region.
17. 17 . The method of claim 16 , wherein an overlap region between the nano-dot region and the channel region is overlapped with the drain electrode.
18. 18 . A memory device comprising: a drain electrode disposed on a semiconductor substrate; a channel region in contact with the drain electrode; a source electrode in contact with the channel region; and a floating gate region in contact with the source electrode and the drain electrode, the floating gate region comprising a nano-dot region comprising at least one nano-dot gate, wherein the drain electrode overlaps the nano-dot region, wherein the nano-dot region overlaps the channel region, wherein the at least one nano-dot gate is configured to receive a charge tunneled from the drain electrode based on a voltage applied to the drain electrode, and wherein the drain electrode comprises: a first electrode in contact with an upper surface of the semiconductor substrate and extending in parallel to the upper surface of the semiconductor substrate, a second electrode in contact with an upper surface of the first electrode and in contact with a lateral side of the floating gate region, and extending perpendicular to the upper surface of the semiconductor substrate, and a third electrode in contact with an upper surface of the second electrode and in contact and overlapping with an upper surface of the floating gate region, and extending in parallel to the upper surface of the semiconductor substrate.
19. 19 . The memory device of claim 18 , wherein: the at least one nano-dot gate is configured to receive an electron tunneled from the drain electrode due to a first voltage applied to the drain electrode; and the at least one nano-dot gate is configured to receive a hole tunneled from the drain electrode due to a second voltage applied to the drain electrode.
20. 20 . The memory device of claim 18 , wherein the channel region is configured to be controlled to be turned on and turned off by the voltage applied to the drain electrode.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of Korean Patent Application No. 10-2021-0134312, filed on Oct. 8, 2021, which application is hereby incorporated herein by reference. TECHNICAL FIELD The present disclosure relates to a memory device including a nano-structure and a method for fabricating the same. BACKGROUND A memory system is a component to store data in various electronic devices, and a non-volatile memory of various memories may store information even if power is cut off. A flash memory of non-volatile memories includes a gate insulator and a gate electrode and an oxide and is thick and rigid. Accordingly, the flash memory requires higher power consumption, and the integration of the flash memory is difficult. In addition, the flash memory may inject electrons or holes into a floating gate using a voltage applied to a gate electrode. As the operation of injecting the electrons or the holes into the floating gate is repeated, an insulating layer included in the floating gate may be deteriorated. As the insulating layer is deteriorated, a leakage current may be caused. As the leakage current is caused, the threshold voltage of the memory device is changed, such that the stored data may be distorted, and the performance of the memory device may be deteriorated. Accordingly, there is required a structure for implementing a smaller memory device and for preventing a leakage current. SUMMARY Embodiments of the present disclosure can solve problems occurring in the prior art while advantages achieved by the prior art are maintained intact. An embodiment of the present disclosure provides a memory device structure having the enhanced degree of integration by skipping a gate electrode. In addition, embodiments of the present disclosure provide a memory device having improved endurance and reliability, as a floating gate of the memory device includes at least one nano-dot gate. The technical problems to be solved by embodiments of the present disclosure are not limited to the aforementioned problems, and any other technical problems not mentioned herein will be clearly understood from the following description by those skilled in the art to which the present disclosure pertains. According to an embodiment of the present disclosure, a memory device may include a drain electrode disposed on a semiconductor substrate, a channel region making contact with the drain electrode, a source electrode making contact with the channel region and a floating gate region making contact with the source electrode and the drain electrode. The floating gate region may include a nano-dot region including at least one nano-dot gate, the drain electrode may be overlapped with the nano-dot region, and the nano-dot region may be overlapped with the channel region. In addition, according to an embodiment, the overlap region between the nano-dot region and the channel region may be overlapped with the drain electrode. In addition, according to an embodiment, the drain electrode may include a first electrode making contact with the semiconductor substrate while extending in parallel to one surface of the semiconductor substrate, a second electrode making contact with the lateral side of the floating gate region while extending perpendicular to one surface of the semiconductor substrate, and a third electrode making contact with the one surface of the floating gate region while extending in parallel to the one surface of the semiconductor substrate. In addition, according to an embodiment, the third electrode may be overlapped with the nano-dot region and the channel region. In addition, according to an embodiment, the channel region may be interposed between the semiconductor substrate and the floating gate region. In addition, according to an embodiment, the channel region may include a first region making contact with the drain electrode while extending in parallel to one surface of the drain electrode, a second region making contact with a lateral side of the floating gate region while extending perpendicularly to the one surface of the drain electrode, and a third region making contact with one surface of the floating gate region while extending in parallel to the one surface of the drain electrode. In addition, according to an embodiment, the third region may be overlapped with the nano-dot region and the drain electrode. In addition, according to an embodiment, the drain electrode may be interposed between the semiconductor substrate and the channel region. In addition, according to an embodiment, the floating gate region may include an insulating layer region to surround the at least one nano-dot gate. In addition, according to an embodiment, the nano-dot gate may be electrically isolated from another nano-dot gate adjacent to the insulating region. In addition, according to an embodiment, the insulating layer region may include at least one selected from the group consisting of boron hexago