US-12622033-B2 - Method of integrating SONOS into HKMG flow

Abstract

A semiconductor device and methods of fabricating the same are disclosed. Generally, the method includes forming a tunnel-dielectric for a memory transistor over a surface of a substrate, forming a nitride charge-trapping layer over the tunnel-dielectric, and forming a gate-dielectric for a field-effect transistor over the surface of the substrate. Forming the gate-dielectric can include performing a number of oxidation processes to form a thick gate-oxide while concurrently forming a blocking-dielectric including an oxide layer over the charge-trapping layer of the memory transistor. In one embodiment, performing the oxidation processes includes performing an in-situ-steam-generation process to form the thick gate-oxide and the oxide layer of the blocking-dielectric, followed by a thermal oxidation process to increase a thickness of the thick gate-oxide and the oxide layer without altering a substantially uniform stoichiometric concentration of nitrogen across a thickness of the charge-trapping layer from the tunnel-dielectric to the blocking-dielectric.

Inventors

• Krishnaswamy Ramkumar
• Venkatraman Prabhakar

Assignees

• Infineon Technologies LLC

Dates

Publication Date

20260505

Application Date

20211217

Claims (20)

1. 1 . A method of fabricating a semiconductor device comprising: forming a tunnel-dielectric for a memory transistor over a surface of a substrate; forming a charge-trapping layer comprising a nitride over the tunnel-dielectric; forming a cap layer directly over the charge-trapping layer and a sacrificial oxide layer over the cap layer; patterning the tunnel-dielectric, the charge-trapping, sacrificial oxide, and cap layers to form a non-volatile (NV) gate stack, wherein the sacrificial oxide and cap layers are completely removed beyond the NV gate stack; removing the sacrificial oxide layer completely and the cap layer at least partially from the NV gate stack; and forming a first gate-dielectric for a first field-effect transistor (FET) over the surface of the substrate, wherein forming the first gate-dielectric comprises performing a number of oxidation processes to form a thick gate-oxide (GOX) while concurrently forming a blocking-dielectric comprising a first oxide layer over the charge-trapping layer of the memory transistor, including performing an in-situ-steam-generation (ISSG) process to form the thick GOX and the first oxide layer of the blocking-dielectric, followed by performing a thermal oxidation process to increase a thickness of the thick GOX and the first oxide layer.
2. 2 . The method of claim 1 wherein the thermal oxidation process is a rapid thermal oxidation (RTO), a dry furnace oxidation process, or a wet furnace oxidation process.
3. 3 . The method of claim 1 wherein performing the number of oxidation processes comprises performing a thermal oxidation process followed by an in-situ-steam-generation (ISSG) process to form the first oxide layer of the blocking-dielectric while increasing a thickness of the thick GOX.
4. 4 . The method of claim 1 wherein forming the first gate-dielectric and forming the blocking-dielectric further comprises depositing a high dielectric constant (high-K) material over the thick GOX and the first oxide layer.
5. 5 . The method of claim 4 wherein the first gate-dielectric is a high voltage (HV) gate-dielectric having a total thickness in a range of 100 to 130 angstroms (Å).
6. 6 . The method of claim 4 further comprising forming a first metal gate over the blocking-dielectric of the memory transistor and a second metal gate over the first gate-dielectric of the first FET.
7. 7 . The method of claim 4 further comprising prior to depositing the high-K material performing an additional oxidation process to form a second oxide layer of a second gate-dielectric for a second FET, wherein performing the additional oxidation process increases a thickness of the thick GOX and the first oxide layer.
8. 8 . The method of claim 7 wherein depositing the high-K material further comprises depositing the high-K material over the second oxide layer to form the second gate-dielectric for the second FET.
9. 9 . The method of claim 8 further comprising forming a metal gate over the second gate-dielectric of the second FET.
10. 10 . The method of claim 1 wherein the first FET is a select transistor of a 2T memory cell and is formed adjacent to the memory transistor.
11. 11 . The method of claim 1 wherein the first FET is a select transistor of a 2T multi-level memory cell (MLC) and is formed adjacent to the memory transistor, and wherein the first gate-dielectric has a thickness sufficient to enable the MLC to operate at voltages of at least 10V.
12. 12 . A method of fabricating a 2T multi-level memory cell (MLC), the method comprising: forming a tunnel-dielectric for a memory transistor over a surface of a substrate; forming a charge-trapping layer comprising a nitride over the tunnel-dielectric; forming a cap layer directly over the charge-trapping layer and a sacrificial oxide layer over the cap layer; patterning the tunnel-dielectric, the charge-trapping, sacrificial oxide, and cap layers to form a non-volatile (NV) gate stack, wherein the sacrificial oxide and cap layers are completely removed beyond the NV gate stack; removing the sacrificial oxide layer completely and the cap layer at least partially from the NV gate stack; performing an in-situ-steam-generation (ISSG) process to form a first oxide layer of a blocking-dielectric over the charge-trapping layer and to concurrently form a second oxide layer of a gate-dielectric for a first field-effect transistor (FET) over the surface of the substrate; and performing, subsequent to the ISSG process, a thermal oxidation process to increase a thickness of the first oxide layer and the second oxide layer.
13. 13 . The method of claim 12 further comprising depositing a high dielectric constant (high-K) material to concurrently form a first high-K layer on the first oxide layer of the blocking-dielectric and a second high-K layer on the second oxide layer of the gate-dielectric.
14. 14 . The method of claim 13 further comprising forming a first metal gate over blocking-dielectric for the memory transistor and a second metal gate over the gate-dielectric of the first FET.
15. 15 . The method of claim 12 wherein the thermal oxidation process is a rapid thermal oxidation (RTO).
16. 16 . The method of claim 12 wherein the thermal oxidation process is a wet or dry furnace oxidation process.
17. 17 . A method of fabricating a memory transistor comprising: forming a tunnel-dielectric over a surface of a substrate; forming a nitride charge-trapping layer over the tunnel-dielectric; forming a cap layer directly over the nitride charge-trapping layer and a sacrificial oxide layer over the cap layer; patterning the tunnel-dielectric, the nitride charge-trapping, sacrificial oxide, and cap layers to form a non-volatile (NV) gate stack, wherein the sacrificial oxide and cap layers are completely removed beyond the NV gate stack; removing the sacrificial oxide layer completely and the cap layer at least partially from the NV gate stack; and performing an in-situ-steam-generation (ISSG) process to form a first oxide layer of a blocking-dielectric over the nitride charge-trapping layer, followed by a thermal oxidation process to increase a thickness of the first oxide layer, wherein the forming and increasing the thickness of the first oxide layer does not alter a substantially uniform stoichiometric concentration of nitrogen across a thickness of the nitride charge-trapping layer from the tunnel-dielectric to the blocking-dielectric.
18. 18 . The method of claim 17 further comprises depositing a high dielectric constant (high-K) material over the oxide layer to form a high-K blocking-layer.
19. 19 . The method of claim 18 further comprising forming a metal gate over the high-K blocking-layer to form a high-K metal gate (HKMG) memory transistor.
20. 20 . The method of claim 17 wherein forming the nitride charge-trapping layer comprises forming a bi-layer nitride charge-trapping layer including a silicon-rich and oxygen-rich bottom oxynitride layer over the tunnel-dielectric and a silicon-rich, oxygen-lean top nitride layer overlying the bottom oxynitride layer.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is claims the benefit of priority under 35 U.S.C. 119(e) to U.S. Provisional Patent Application Ser. No. 63/244,316, filed Sep. 15, 2021, which is incorporated by reference herein in its entirety. TECHNICAL FIELD This disclosure relates generally to semiconductor devices, and more particularly to analog and digital memory devices including embedded or integrally formed silicon-oxide-nitride-oxide-silicon (SONOS) memory transistors and high voltage transistors, and methods for fabricating the same. BACKGROUND Flash or non-volatile memory (NVM) devices typically include a grid or an array of storage elements or cells. In one particular embodiment, each storage cell may include at least one charge-trapping field effect transistor (FET) or memory transistor and a select transistor, and a number of peripheral circuits including input/output (I/O) transistors and logic or core transistors to read from and write to the array. The memory transistors generally include a charge-trapping or charge storage layer that trap charge between a control gate (CG) and channel to change a threshold voltage (Vt) of the transistor to store data. The select transistors to activate the memory transistor to support program and erase operations. There are two types of charge-trapping memory transistors, a floating-gate (FG) transistor in which the charge is trapped in an electrically isolated conductive charge trapping layer, typically a polysilicon layer, is sandwiched between the CG and channel, and a silicon-oxide-nitride-oxide-silicon (SONOS) transistor in which the charge is trapped in a non-conductive, typically a silicon-nitride (SiN) layer, interposed between a lower or tunnel oxide layer and a top or blocking oxide layer, all between the CG and channel. SONOS memory transistors are considered more reliable as the non-conductive nature of the nitride charge trapping layer flash makes it more tolerant of defects in the upper or lower oxide, which could discharge the entire polysilicon charge trapping layer of the floating gate transistor. An increasing number of applications, such as artificial intelligence (AI) and machine learning (ML), require increasing amounts of data storage and using memory devices for inferencing function, such as multiply-accumulate (MAC) operations. One way of meeting this demand is through the use of multi-level cell (MLC) in which the memory transistor is capable of storing more than a single bit of information or a single binary bit of information by storing varying amount of charge to represent different analog values, each of which results in a different threshold voltage and determines the state or analog value of data stored the MLC. For example, a MLC memory transistor capable of holding four different levels of charge, from fully programmed to partially programed, partially erased or fully erased, can yield two bits of information which can be interpreted as four distinct states: 00, 01, 10, or 11. Alternatively or additionally, it may present four distinct analog values: 0, 1, 2, or 3. Because, the memory transistor in a MLC requires a larger range of threshold voltages or a larger Vt window, it typically operates at higher gate voltages than memory transistors in single or binary level cells, meaning that the select transistor, as well as many of the transistors in the peripheral circuits, must also be high voltage (HV) transistors capable of operating at voltages of about 10 volts or more. In MLC using FG memory transistors this can be readily accomplished by increasing a thickness of a gate oxide between a gate and the channel of the HV transistors. However, increasing a thickness of a gate oxide of the select transistor or other transistors in memory cells including SONOS memory transistors is problematic since conventional oxidation processes at high temperatures, used to form thick gate oxides can result in non-homogenous distribution of SiN charge-traps throughout a vertical thickness of the charge-trapping layer, rendering it unsuitable for MLC operations. Such integration of SONOS multi-level memory cells is particularly problematic when the memory array is included in an embedded flash device (eFlash) further including other HV, I/O, and core transistors. Accordingly, there is a need for Flash or NVM devices including multi-level memory cells with SONOS memory transistors and HV transistors embedded or integrally formed on a single substrate, and methods for fabricating the same. SUMMARY A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device is particularly useful in forming memory transistor and select transistor of a two-transistor (2T) multi-level memory cell (MLC) in which a gate-dielectric of the select transistor has a thickness sufficient to enable the MLC to operate at voltages up to and exceeding 10V. Generally, the method includes forming a tunnel-dielectric for a memory