US-12622034-B2 - Semiconductor transistor structure having an epitaxial oxide spacer layer

Abstract

A semiconductor structure includes a nanosheet channel stack disposed on a semiconductor substrate. The nanosheet channel stack includes one or more layers of a semiconducting material providing nanosheet channels for one or more nanosheet field-effect transistors and an insulator layer as the bottom most layer disposed on the semiconductor substrate. The semiconductor structure further includes an epitaxial oxide spacer layer disposed on outer ends of a bottom surface of the insulator layer and extending downwardly into the substrate; shallow trench isolation regions disposed adjacent the nanosheet channel stack and extending downwardly from a top surface of the semiconductor substrate, wherein a portion of each of the shallow trench isolation regions is disposed on an outer sidewall of the respective epitaxial oxide spacer layer; and a gate surrounding the nanosheet channel stack and on a top surface of each of the shallow trench isolation regions.

Inventors

• Jennifer Toy
• Alexander Reznicek
• Jingyun Zhang
• Sagarika Mukesh

Assignees

• INTERNATIONAL BUSINESS MACHINES CORPORATION

Dates

Publication Date

20260505

Application Date

20221130

Claims (20)

1. 1 . A semiconductor structure, comprising: a nanosheet channel stack disposed on a semiconductor substrate, the nanosheet channel stack comprising one or more layers of a semiconducting material providing nanosheet channels for one or more nanosheet field-effect transistors and an insulator layer as the bottom most layer disposed on the semiconductor substrate; a first epitaxial oxide spacer layer and a second epitaxial oxide spacer layer disposed on respective outer ends of a bottom surface of the insulator layer and extending downwardly into the semiconductor substrate, wherein the semiconductor substrate is disposed between the first epitaxial oxide spacer layer and the second epitaxial oxide spacer layer; shallow trench isolation regions disposed adjacent the nanosheet channel stack and extending downwardly from a top surface of the semiconductor substrate, wherein a portion of each of the shallow trench isolation regions is disposed on an outer sidewall of the respective epitaxial oxide spacer layer; and a gate surrounding the nanosheet channel stack and on a top surface of each of the shallow trench isolation regions.
2. 2 . The semiconductor structure according to claim 1 , wherein the insulator layer is a bottom dielectric insulator layer.
3. 3 . The semiconductor structure according to claim 1 , wherein the semiconductor substrate is silicon and the epitaxial oxide spacer layer comprises a layer of a mixed rare earth oxide, the mixed rare earth oxide being single crystal and lattice-matched to silicon.
4. 4 . The semiconductor structure according to claim 3 , wherein the mixed rare earth oxide comprises a compound having a chemical formula (A x B 1-x ) 2 O 3 , wherein A represents a first rare earth element and B represents a second rare earth element.
5. 5 . The semiconductor structure according to claim 3 , wherein the mixed rare earth oxide comprises (La x Y 1-x ) 2 O 3 and x is 0.33.
6. 6 . The semiconductor structure according to claim 3 , wherein the mixed rare earth oxide comprises a ternary mixed rare earth oxide.
7. 7 . The semiconductor structure according to claim 3 , wherein a lattice constant of the mixed rare earth oxide is twice a lattice constant of the semiconductor substrate.
8. 8 . The semiconductor structure according to claim 1 , wherein a bottom surface of the shallow trench isolation regions is below a bottom surface of the epitaxial oxide spacer layer.
9. 9 . The semiconductor structure according to claim 1 , wherein the semiconductor substrate is disposed between inner sidewalls of the respective epitaxial oxide spacer layer and on the bottom surface of the insulator layer.
10. 10 . A semiconductor structure, comprising: a first nanosheet channel stack disposed on a semiconductor substrate and a second nanosheet channel stack adjacent the first nanosheet channel stack, the first and second nanosheet channel stacks each comprising one or more layers of a semiconducting material providing nanosheet channels for one or more nanosheet field-effect transistors and an insulator layer as the bottom most layer disposed on the semiconductor substrate; a first epitaxial oxide spacer layer and a second epitaxial oxide spacer layer disposed on respective outer ends of a bottom surface of the insulator layer of each of the first and second nanosheet channel stacks and extending downwardly into the semiconductor substrate, wherein the semiconductor substrate is disposed between the first epitaxial oxide spacer layer and the second epitaxial oxide spacer layer; shallow trench isolation regions disposed adjacent each of the first and second nanosheet channel stacks and extending downwardly from a top surface of the semiconductor substrate, wherein a portion of each of the shallow trench isolation regions is disposed on an outer sidewall of the respective epitaxial oxide spacer layer; and a gate surrounding each of the first and second nanosheet channel stacks and on a top surface of each of the shallow trench isolation regions.
11. 11 . The semiconductor structure according to claim 10 , wherein the insulator layer is a bottom dielectric insulator layer.
12. 12 . The semiconductor structure according to claim 10 , wherein the semiconductor substrate is silicon and the epitaxial oxide spacer layer comprises a layer of a mixed rare earth oxide, the mixed rare earth oxide being single crystal and lattice-matched to silicon.
13. 13 . The semiconductor structure according to claim 12 , wherein a lattice constant of the mixed rare earth oxide is twice a lattice constant of the semiconductor substrate.
14. 14 . The semiconductor structure according to claim 12 , wherein the mixed rare earth oxide comprises a compound having a chemical formula (A x B 1-x ) 2 O 3 , wherein A represents a first rare earth element and B represents a second rare earth element.
15. 15 . The semiconductor structure according to claim 12 , wherein the mixed rare earth oxide comprises (La x Y 1-x ) 2 O 3 and x is 0.33.
16. 16 . The semiconductor structure according to claim 10 , wherein a bottom surface of the shallow trench isolation regions is below a bottom surface of the epitaxial oxide spacer layer.
17. 17 . The semiconductor structure according to claim 10 , wherein the semiconductor substrate is disposed between inner sidewalls of the respective epitaxial oxide spacer layer and on the bottom surface of the insulator layer.
18. 18 . An integrated circuit, comprising: one or more semiconductor structures, wherein at least one of the one or more semiconductor structures comprises: a nanosheet channel stack disposed on a semiconductor substrate, the nanosheet channel stack comprising one or more layers of a semiconducting material providing nanosheet channels for one or more nanosheet field-effect transistors and an insulator layer as the bottom most layer disposed on the semiconductor substrate; a first epitaxial oxide spacer layer and a second epitaxial oxide spacer layer disposed on respective outer ends of a bottom surface of the insulator layer and extending downwardly into the semiconductor substrate, wherein the semiconductor substrate is disposed between the first epitaxial oxide spacer layer and the second epitaxial oxide spacer layer; shallow trench isolation regions disposed adjacent the nanosheet channel stack and extending downwardly from a top surface of the semiconductor substrate, wherein a portion of each of the shallow trench isolation regions is disposed on an outer sidewall of the respective epitaxial oxide spacer layer; and a gate surrounding the nanosheet channel stack and on a top surface of each of the shallow trench isolation regions.
19. 19 . The integrated circuit according to claim 18 , wherein the semiconductor substrate is silicon and the epitaxial oxide spacer layer comprises a layer of a mixed rare earth oxide, the mixed rare earth oxide being single crystal and lattice-matched to silicon.
20. 20 . The integrated circuit according to claim 19 , wherein the mixed rare earth oxide comprises a compound having a chemical formula (A x B 1-x ) 2 O 3 , wherein A represents a first rare earth element and B represents a second rare earth element.

Description

BACKGROUND A field-effect transistor (FET) is a transistor having a source, a gate, and a drain, and having action that depends on the flow of carriers (electrons or holes) along a channel that runs between the source and drain. Current through the channel between the source and drain may be controlled by a transverse electric field under the gate. FETs are widely used for switching, amplification, filtering, and other tasks. FETs include metal-oxide-semiconductor FETs (MOSFETs). Complementary MOS (CMOS) devices are widely used, where both n-type and p-type transistors (nFET and pFET) are used to form logic and other circuitry. Source and drain regions of a FET are typically formed by adding dopants to target regions of a semiconductor body on either side of a channel, with the gate being formed above the channel. The gate includes a gate dielectric over the channel and a gate conductor over the gate dielectric. The gate dielectric is an insulator material that prevents large leakage current from flowing into the channel when voltage is applied to the gate conductor while allowing applied gate voltage to produce a transverse electric field in the channel. SUMMARY Illustrative embodiments of the present application include techniques for use in semiconductor manufacture. In an illustrative embodiment, a semiconductor structure comprises a nanosheet channel stack disposed on a semiconductor substrate. The nanosheet channel stack comprises one or more layers of a semiconducting material providing nanosheet channels for one or more nanosheet field-effect transistors and an insulator layer as the bottom most layer disposed on the semiconductor substrate. The semiconductor structure further comprises an epitaxial oxide spacer layer disposed on outer ends of a bottom surface of the insulator layer and extending downwardly into the semiconductor substrate. The semiconductor structure further comprises shallow trench isolation regions disposed adjacent the nanosheet channel stack and extending downwardly from a top surface of the semiconductor substrate. A portion of each of the shallow trench isolation regions is disposed on an outer sidewall of the respective epitaxial oxide spacer layer. The semiconductor structure further comprises a gate surrounding the nanosheet channel stack and on a top surface of each of the shallow trench isolation regions. The semiconductor structure of the illustrative embodiment advantageously provides protection from potential shorts between a replacement metal gate and the semiconductor substrate by utilizing an epitaxial oxide spacer layer. In one or more additional illustrative embodiments, as may be combined with the preceding paragraphs, the insulator layer is a bottom dielectric insulator layer. In one or more additional illustrative embodiments, as may be combined with the preceding paragraphs, the semiconductor substrate is silicon and the epitaxial oxide spacer layer comprises a layer of a mixed rare earth oxide, the mixed rare earth oxide being single crystal and lattice-matched to silicon. In one or more additional illustrative embodiments, as may be combined with the preceding paragraphs, the mixed rare earth oxide comprises a compound having a chemical formula (AxB1-x)2O3, wherein A represents a first rare earth element and B represents a second rare earth element. In one or more additional illustrative embodiments, as may be combined with the preceding paragraphs, the mixed rare earth oxide comprises (LaxY1-x)2O3. In one or more additional illustrative embodiments, as may be combined with the preceding paragraphs, the mixed rare earth oxide comprises a ternary mixed rare earth oxide. In one or more additional illustrative embodiments, as may be combined with the preceding paragraphs, a lattice constant of the mixed rare earth oxide is twice a lattice constant of the semiconductor substrate. In one or more additional illustrative embodiments, as may be combined with the preceding paragraphs, a bottom surface of the shallow trench isolation regions is below a bottom surface of the epitaxial oxide spacer layer. In another exemplary embodiment, a semiconductor structure comprises a first nanosheet channel stack disposed on a semiconductor substrate and a second nanosheet channel stack adjacent the first nanosheet channel stack. The first and second nanosheet channel stacks each comprise one or more layers of a semiconducting material providing nanosheet channels for one or more nanosheet field-effect transistors and an insulator layer as the bottom most layer disposed on the semiconductor substrate. The semiconductor structure further comprises an epitaxial oxide spacer layer disposed on outer ends of a bottom surface of the insulator layer of each of the first and second nanosheet channel stacks and extending downwardly into the semiconductor substrate. The semiconductor structure further comprises shallow trench isolation regions disposed adjacent each of the first and seco