US-12622035-B2 - Semiconductor devices

Abstract

A semiconductor device includes first and second gate structures, first and second contact plug structures and a first wiring on a substrate. The first and second source/drain layers are formed on portions of the substrate adjacent to the first and second gate structures, respectively. The first and second contact plug structures are formed on the first and second source/drain layers, respectively. The first wiring contacts an upper surface of the first gate structure. The first gate structure includes a first gate electrode and a first gate insulation pattern on a lower surface and a sidewall of the first gate electrode. The second gate structure includes a second gate electrode and a second gate insulation pattern on a lower surface and a sidewall of the second gate electrode. The upper surface of the second gate electrode is lower than an upper surface of the first gate electrode.

Inventors

• Hongsik SHIN
• Sungwoo Kang
• Dongkwon Kim
• Hyonwook RA
• Jeongyeon Seo
• KyungYub JEON

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260505

Application Date

20230209

Priority Date

20220427

Claims (20)

1. 1 . A semiconductor device, comprising: first and second gate structures on a substrate; first and second source/drain layers on portions of the substrate adjacent to the first and second gate structures, respectively; first and second contact plug structures on the first and second source/drain layers, respectively; and a first wiring contacting an upper surface of the first gate structure, wherein the first gate structure includes: a first gate electrode; and a first gate insulation pattern on a lower surface and a sidewall of the first gate electrode, wherein the second gate structure includes: a second gate electrode; and a second gate insulation pattern on a lower surface and a sidewall of the second gate electrode, and wherein the second gate electrode has a smaller vertical dimension than the first gate electrode.
2. 2 . The semiconductor device as claimed in claim 1 , wherein an uppermost surface of the second gate insulation pattern is lower than an upper surface of the second gate electrode.
3. 3 . The semiconductor device as claimed in claim 1 , wherein an uppermost surface of the first gate insulation pattern is substantially coplanar with an upper surface of the first gate electrode.
4. 4 . The semiconductor device as claimed in claim 1 , further comprising: a gate spacer on a sidewall of the second gate structure, wherein an uppermost surface of the gate spacer is substantially coplanar with an upper surface of the second gate electrode.
5. 5 . The semiconductor device as claimed in claim 1 , wherein the second contact plug structure includes: a first conductive pattern including a first metal; and a first barrier pattern on a lower surface and a sidewall of the first conductive pattern, and wherein an uppermost surface of the first barrier pattern is lower than an upper surface of the first conductive pattern.
6. 6 . The semiconductor device as claimed in claim 5 , further comprising: a plug spacer on a sidewall of the second contact plug structure, wherein an uppermost surface of the plug spacer is substantially coplanar with the upper surface of the first conductive pattern.
7. 7 . The semiconductor device as claimed in claim 5 , wherein the first contact plug structure includes: a second conductive pattern including the first metal; a second barrier pattern on a lower surface and a sidewall of the second conductive pattern; and a third conductive pattern contacting an upper surface of the second conductive pattern and an upper surface of the second barrier pattern, the third conductive pattern including a second metal different from the first metal, and wherein an uppermost surface of the second barrier pattern is lower than the upper surface of the second conductive pattern.
8. 8 . The semiconductor device as claimed in claim 7 , wherein the upper surface of the first conductive pattern is lower than the upper surface of the second conductive pattern.
9. 9 . The semiconductor device as claimed in claim 7 , further comprising: a second wiring contacting an upper surface of the first contact plug structure.
10. 10 . The semiconductor device as claimed in claim 1 , further comprising: an isolation pattern covering a lower sidewall of an active pattern provided at an upper surface of the substrate, wherein the active pattern extends in a first direction substantially parallel to the upper surface of the substrate and protrudes past the upper surface of the substrate in a third direction substantially perpendicular to the upper surface of the substrate, wherein each of the first and second gate structures is disposed on the active pattern and the isolation pattern.
11. 11 . The semiconductor device as claimed in claim 10 , wherein: the active pattern is one of a plurality of active patterns spaced apart from each other in a second direction substantially parallel to the upper surface of the substrate and crossing the first direction, the second gate structure extends in the second direction and is divided, in the second direction, into individual gate structures by a division pattern, the second gate insulation pattern is disposed on surfaces of the plurality of active patterns, an upper surface of the isolation pattern and a sidewall of the division pattern, the second gate electrode is disposed on the second gate insulation pattern, and an uppermost surface of the second gate insulation pattern is lower than an upper surface of the division pattern.
12. 12 . The semiconductor device as claimed in claim 10 , wherein: the active pattern is one of a plurality of active patterns spaced apart from each other in a second direction substantially parallel to the upper surface of the substrate and crossing the first direction, the second source/drain layer is one of a plurality of second source/drain layers, each second source/drain layer of the plurality of second source/drain layers is disposed on a corresponding active pattern of the plurality of active patterns, the semiconductor device further comprises a division pattern between neighboring second source/drain layers, in the second direction, of the plurality of second source/drain layers, the second contact plug structure on the second source/drain layers includes: a conductive pattern including metal; and a barrier pattern on a lower surface and a sidewall of the conductive pattern, and an uppermost surface of the barrier pattern is lower than an upper surface of the division pattern.
13. 13 . The semiconductor device as claimed in claim 10 , further comprising: a plurality of first channels spaced apart from each other in the third direction on the active pattern, each first channel of the plurality of first channels extending in the first direction; and a plurality of second channels spaced apart from each other in the third direction on the active pattern, each second channel of the plurality of second channels extending in the first direction, wherein the first gate structure covers lower and upper surfaces and each of opposite sidewalls in a second direction of each first channel of the plurality of first channels, the second direction substantially parallel to the upper surface of the substrate and crossing the first direction, and wherein the second gate structure covers lower and upper surfaces and each of opposite sidewalls in the second direction of each second channel of the plurality of second channels.
14. 14 . A semiconductor device, comprising: a gate structure on a substrate; first and second source/drain layers on portions of the substrate adjacent to the gate structure; first and second contact plug structures directly on the first and second source/drain layers, respectively; a first wiring contacting an upper surface of the first contact plug structure; and an insulation pattern contacting an uppermost surface of the second contact plug structure, wherein the uppermost surface of the second contact plug structure is lower than an uppermost surface of the first contact plug structure.
15. 15 . The semiconductor device as claimed in claim 14 , wherein the first contact plug structure includes: a first conductive pattern including a first metal; a first barrier pattern on a lower surface and a sidewall of the first conductive pattern; and a second conductive pattern contacting an upper surface of the first conductive pattern and an upper surface of the first barrier pattern, wherein the second contact plug structure includes: a third conductive pattern including the first metal; and a second barrier pattern on a lower surface and a sidewall of the third conductive pattern, wherein an uppermost surface of the first barrier pattern is lower than an upper surface of the first conductive pattern, and wherein an uppermost surface of the second barrier pattern is lower than an upper surface of the third conductive pattern.
16. 16 . The semiconductor device as claimed in claim 15 , wherein the upper surface of the third conductive pattern is lower than the upper surface of the first conductive pattern.
17. 17 . The semiconductor device as claimed in claim 15 , further comprising: a plug spacer on a sidewall of the second contact plug structure, wherein an uppermost surface of the plug spacer is substantially coplanar with the upper surface of the third conductive pattern.
18. 18 . A semiconductor device, comprising: first and second gate structures on a substrate; first and second source/drain layers on portions of the substrate adjacent to the first and second gate structures, respectively; first and second contact plug structures on the first and second source/drain layers, respectively; a first wiring contacting an upper surface of the first gate structure; a second wiring contacting an upper surface of the first contact plug structure; and an insulation pattern contacting an upper surface of the second gate structure and an upper surface of the second contact plug structure, wherein the upper surface of the second gate structure is lower than the upper surface of the first gate structure, and wherein the upper surface of the second contact plug structure is lower than the upper surface of the first contact plug structure.
19. 19 . The semiconductor device as claimed in claim 18 , further comprising: a gate spacer on a sidewall of the second gate structure, wherein the second gate structure includes: a gate electrode; and a gate insulation pattern on a lower surface and a sidewall of the gate electrode, and wherein an uppermost surface of the gate spacer is higher than an upper surface of the gate insulation pattern.
20. 20 . The semiconductor device as claimed in claim 18 , further comprising: a plug spacer on a sidewall of the second contact plug structure, wherein the second contact plug structure includes: a conductive pattern including metal; and a barrier pattern on a lower surface and a sidewall of the conductive pattern, and wherein an uppermost surface of the plug spacer is higher than an upper surface of the barrier pattern.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims priority under 35 USC § 119 to Korean Patent Application No. 10-2022-0051760, filed on Apr. 27, 2022 in the Korean Intellectual Property Office (KIPO), the contents of which are herein incorporated by reference in their entirety. BACKGROUND 1. Field Example embodiments relate to semiconductor devices. More particularly, example embodiments relate to semiconductor devices having contact plugs. 2. Description of the Related Art In a logic device, a contact plug and a via structure may be formed to connect a gate structure and a source/drain layer to upper wirings for applying electrical signals thereto. However, a total resistance of the gate structure, the source/drain layer, the contact plug structure and the via structure increases due to a contact resistance between the gate structure and the contact plug structure or between the source/drain layer and the contact plug structure. Additionally, the gate structure and the contact plug structure may be electrically shorted with each other, or the contact plug structure and the via structure may be electrically shorted with each other. SUMMARY Example embodiments provide a semiconductor device having enhanced characteristics. According to example embodiments, there is provided a semiconductor device. The semiconductor device may include first and second gate structures, first and second contact plug structures, and a first wiring. The first and second gate structures may be formed on a substrate. The first and second source/drain layers may be formed on portions of the substrate adjacent to the first and second gate structures, respectively. The first and second contact plug structures may be formed on the first and second source/drain layers, respectively. The first wiring may contact an upper surface of the first gate structure. The first gate structure may include a first gate electrode and a first gate insulation pattern on a lower surface and a sidewall of the first gate electrode. The second gate structure may include a second gate electrode and a second gate insulation pattern on a lower surface and a sidewall of the second gate electrode. The upper surface of the second gate electrode may be lower than an upper surface of the first gate electrode. According to example embodiments, there is provided a semiconductor device. The semiconductor device may include a gate structure, first and second source/drain layers, first and second contact plug structures, a first wiring and an insulation pattern. The gate structure may be formed on a substrate. The first and second source/drain layers may be formed on portions of the substrate adjacent to the gate structure. The first and second contact plug structures may be formed on the first and second source/drain layers, respectively. The first wiring may contact an upper surface of the first contact plug structure. The insulation pattern may contact an upper surface of the second contact plug structure. An uppermost surface of the second contact plug structure may be lower than an upper surface of the first contact plug structure. According to example embodiments, there is provided a semiconductor device. The semiconductor device may include first and second gate structures on a substrate, first and second source/drain layers on portions of the substrate adjacent to the first and second gate structures, respectively, first and second contact plug structures on the first and second source/drain layers, respectively, a first wiring contacting an upper surface of the first gate structure, a second wiring contacting an upper surface of the first contact plug structure, and an insulation pattern contacting an upper surface of the second gate structure and an upper surface of the second contact plug structure. An upper surface of the second gate structure may be lower than an upper surface of the first gate structure, and an upper surface of the second contact plug structure may be lower than an upper surface of the first contact plug structure. In the semiconductor device in accordance with example embodiments, a total contact resistance between the gate structure or the contact plug structure and the upper wiring may decrease. Additionally, the electrical short between the contact plug structure and the gate structure may decrease. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view illustrating a semiconductor device in accordance with example embodiments, FIG. 2 is a cross-sectional view taken along line A-A′ of FIG. 1, FIG. 3 is a cross-sectional view taken along line B-B′ of FIG. 1, and FIG. 4 is a cross-sectional view taken along line C-C′ of FIG. 1. FIGS. 5, 8, 11, 14, 18, 21, 26 and 29 are plan views illustrating a method of manufacturing a semiconductor device in accordance with example embodiments; FIGS. 6 and 7 are cross-sectional views taken along lines A-A′ and B-B′ of FIG. 5, respectively; FIGS. 9 and 10 are cross-sectional views taken a