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US-12622036-B2 - Semiconductor device

US12622036B2US 12622036 B2US12622036 B2US 12622036B2US-12622036-B2

Abstract

A semiconductor device includes a substrate, a source electrode, a drain electrode, a first gate electrode extending in a first direction and provided between the source electrode and the drain electrode, a second gate electrode provided in a region between the source electrode and the drain electrode positioned in the first direction from the first gate electrode, a gate pad provided so as to dispose the first gate electrode between the gate pad and the second gate electrode, and electrically connected to the first gate electrode, a first gate line provided above the source electrode, a second gate line provided above the source electrode and extending in a second direction that crosses the first direction, and a first guard metal layer provided between the second gate line and the drain electrode, and having at least a portion provided between the drain electrode and the source electrode.

Inventors

  • Taizo Tatsumi
  • Masahiro Tanomura

Assignees

  • SUMITOMO ELECTRIC INDUSTRIES, LTD.

Dates

Publication Date
20260505
Application Date
20231003
Priority Date
20221007

Claims (10)

  1. 1 . A semiconductor device comprising: a substrate; a source electrode extending in a first direction and provided on the substrate; a drain electrode extending in the first direction and provided on the substrate; a first gate electrode extending in the first direction and provided on the substrate between the source electrode and the drain electrode; a second gate electrode extending in the first direction and provided in a region on the substrate that is between the source electrode and the drain electrode and that is positioned in the first direction from the first gate electrode; a gate pad provided so as to dispose the first gate electrode between the gate pad and the second gate electrode, and electrically connected to the first gate electrode; a first gate line provided above the source electrode and opposite to the substrate with respect to the source electrode, and extending in the first direction; a second gate line provided above the source electrode, extending in a second direction that crosses the first direction, having a first end connected to the first gate line, and having a second end opposite to the first end, the second end being electrically connected to the second gate electrode outside the source electrode; and a first guard metal layer provided between the second gate line and the drain electrode, and having at least a portion provided between the drain electrode and the source electrode, the first guard metal layer being electrically connected to the source electrode.
  2. 2 . The semiconductor device according to claim 1 , wherein the first guard metal layer is provided so as to surround a portion of the second gate line positioned outside the source electrode from the first direction, a direction opposite to the first direction, and the second direction.
  3. 3 . The semiconductor device according to claim 2 , wherein the first guard metal layer has a first end electrically connected to the source electrode in a region apart from the second gate line in the first direction, and a second end electrically connected to the source electrode in a region apart from the second gate line in the direction opposite to the first direction.
  4. 4 . The semiconductor device according to claim 1 , further comprising: a second guard metal layer provided between the first gate line and the drain electrode, extending in the first direction, and having at least a portion provided above the source electrode, the second guard metal layer being electrically connected to the source electrode.
  5. 5 . The semiconductor device according to claim 1 , further comprising: an insulating film provided on the substrate so as to cover the source electrode, the drain electrode, the first gate electrode, and the second gate electrode, wherein the first gate line, the second gate line, and the first guard metal layer are provided on the insulating film.
  6. 6 . The semiconductor device according to claim 5 , further comprising: a first via line penetrating through the insulating film and electrically connecting the source electrode and the first guard metal layer.
  7. 7 . The semiconductor device according to claim 5 , further comprising: a second via line penetrating through the insulating film and electrically connecting the second gate electrode and the second gate line.
  8. 8 . The semiconductor device according to claim 1 , further comprising: a source wall having at least a portion that is provided between the second gate electrode and the drain electrode and extends in the first direction, wherein the first guard metal layer is electrically connected to the source wall outside the source electrode.
  9. 9 . The semiconductor device according to claim 1 , wherein the first gate electrode and the second gate electrode are apart from each other on an upper surface of the substrate in the first direction.
  10. 10 . The semiconductor device according to claim 1 , wherein in a direction normal to an upper surface of the substrate, the source electrode and the drain electrode have a thickness larger than a thickness of the first gate electrode and the second gate electrode.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This application claims priority based on Japanese Patent Application No. 2022-162621 filed on Oct. 7, 2022, and the entire contents of the Japanese patent application are incorporated herein by reference. TECHNICAL FIELD The present disclosure relates to a semiconductor device. BACKGROUND In a field effect transistor (FET) having finger-shaped source electrodes, gate electrodes, and drain electrodes, it is known that a plurality of unit FETs each having a source electrode, a gate electrode, and a drain electrode are arranged in an extending direction of the electrodes (for example, PTL 1: Japanese Unexamined Patent Application Publication No. 2002-299351, PTL 2: U.S. Pat. No. 9,786,660). SUMMARY An embodiment of the present disclosure is about a semiconductor device includes, a substrate, a source electrode extending in a first direction and provided on the substrate, a drain electrode extending in the first direction and provided on the substrate, a first gate electrode extending in the first direction and provided on the substrate between the source electrode and the drain electrode, a second gate electrode extending in the first direction and provided in a region on the substrate that is between the source electrode and the drain electrode and that is positioned in the first direction from the first gate electrode, a gate pad provided so as to dispose the first gate electrode between the gate pad and the second gate electrode, and electrically connected to the first gate electrode, a first gate line provided above the source electrode and opposite to the substrate with respect to the source electrode, and extending in the first direction, a second gate line provided above the source electrode, extending in a second direction that crosses the first direction, having a first end connected to the first gate line, and having a second end opposite to the first end, the second end being electrically connected to the second gate electrode outside the source electrode, and a first guard metal layer provided between the second gate line and the drain electrode, and having at least a portion provided between the drain electrode and the source electrode, the first guard metal layer being electrically connected to the source electrode. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an amplifier using an FET according to a first embodiment. FIG. 2 is a plan view of an FET according to the first embodiment. FIG. 3 is an enlarged plan view of a range D in FIG. 2. FIG. 4 is an enlarged plan view of a range E in FIG. 2. FIG. 5 is a cross-sectional view taken along a line A-A in FIG. 3. FIG. 6 is a cross-sectional view taken along a line B-B in FIG. 3. FIG. 7 is a cross-sectional view taken along a line C-C in FIG. 3. FIG. 8 is a plan view of a semiconductor device according to a first comparative example. FIG. 9 is an enlarged plan view of a range D in FIG. 8. FIG. 10 is a cross-sectional view taken along a line A-A in FIG. 9. FIG. 11 is a cross-sectional view taken along a line B-B in FIG. 9. FIG. 12 is an enlarged plan view of a semiconductor device according to a first modification of the first embodiment. FIG. 13 is a cross-sectional view of a semiconductor device according to a second modification of the first embodiment. FIG. 14 is a plan view of an FET according to a second embodiment. FIG. 15 is a plan view of an FET according to the second embodiment. FIG. 16 is a cross-sectional view taken along lines A-A in FIGS. 14 and 15. FIG. 17 is a cross-sectional view taken along lines B-B in FIGS. 14 and 15. DETAILED DESCRIPTION In each of the PTLs 1 and 2, the width of the gate electrode in the unit FET can be reduced by arranging a plurality of unit FETs in the extending direction of the electrode. Therefore, a gate resistance can be suppressed. However, a gate line that electrically connects a gate pad and a gate electrode away from the gate pad is provided above the unit FET. At a position where the gate line approaches the drain electrode, a parasitic capacitance between the gate line and the drain electrode is increased, and characteristics such as gain are deteriorated. The present disclosure has been made in view of the above problems, and an object of the present disclosure is to suppress deterioration of characteristics. DETAILS OF EMBODIMENTS OF PRESENT DISCLOSURE First, the contents of embodiments of the present disclosure will be listed and explained. (1) A semiconductor device includes, a substrate, a source electrode extending in a first direction and provided on the substrate, a drain electrode extending in the first direction and provided on the substrate, a first gate electrode extending in the first direction and provided on the substrate between the source electrode and the drain electrode, a second gate electrode extending in the first direction and provided in a region on the substrate that is between the source electrode and the drain electr