US-12622037-B2 - Gate cut subsequent to replacement gate

Abstract

A semiconductor device includes a first gate upon a semiconductor substrate and a second gate upon the semiconductor substrate in line with the first gate. A gate cut dielectric is between the first gate and the second gate. A first gate cap is upon a top surface of the first gate and a second gate cap is upon a top surface of the second gate. A gate cut multilayer structure is between the first gate cap and the second gate cap. The gate cut multilayer structure includes a dielectric between a first substantially vertical spacer and a second substantially vertical spacer. A first sidewall of the multilayer structure is coplanar with an end of the first gate and a second opposing sidewall of the multilayer structure is coplanar with an end of the second gate.

Inventors

• Chanro Park
• Andrew M. Greene
• Andrew Gaul
• Ruilong Xie

Assignees

• INTERNATIONAL BUSINESS MACHINES CORPORATION

Dates

Publication Date

20260505

Application Date

20211111

Claims (20)

1. 1 . A semiconductor device comprising: a first gate structure upon a first dielectric material; a gate cut region that separates the first gate structure into at least a first gate conductor and a second gate conductor; a gate cut dielectric filling the gate cut region, wherein the gate cut dielectric is directly upon an end of the first gate conductor and directly upon an end of the second gate conductor, wherein the gate cut dielectric is a different material from the first dielectric material; a first gate cap upon a top surface of at least the first gate conductor and a second gate cap upon at least a top surface of the second gate conductor; and a gate cut multilayer structure directly upon a top surface of the gate cut dielectric and between the first gate cap and the second gate cap, the gate cut multilayer structure comprising an inner dielectric composed of the first dielectric material between a first high-k dielectric spacer and a second high-k dielectric spacer, wherein a first sidewall of the gate cut multilayer structure is coplanar with the end of the first gate conductor and a second opposing sidewall of the gate cut multilayer structure is coplanar with the end of the second gate conductor, and wherein respective top surfaces of the first gate cap, the second gate cap, and the gate cut multilayer structure are substantially coplanar.
2. 2 . The semiconductor device of claim 1 , wherein a bottom surface of the gate cut multilayer structure is above the top surface of the first gate conductor and is above the top surface of the second gate conductor.
3. 3 . The semiconductor device of claim 1 , wherein the first sidewall of the gate cut multilayer structure is coplanar with an end of the first gate cap and the second opposing sidewall of the gate cut multilayer structure is coplanar with an end of the second gate cap.
4. 4 . The semiconductor device of claim 1 , further comprising: a second gate structure upon the first dielectric material between a lower gate spacer and an upper gate spacer.
5. 5 . The semiconductor device of claim 4 , wherein a bottom surface of the gate cut multilayer structure is coplanar with a bottom surface of the upper gate spacer.
6. 6 . The semiconductor device of claim 4 , wherein a bottom surface of the gate cut multilayer structure is coplanar with a top surface of the lower gate spacer.
7. 7 . The semiconductor device of claim 4 , wherein a thickness of the first high-k dielectric spacer is the same as a thickness of the second high-k dielectric spacer and is the same as a thickness of the upper gate spacer.
8. 8 . The semiconductor device of claim 4 , further comprising: a source and/or drain (S/D) contact between the first gate structure and the second gate structure.
9. 9 . A semiconductor device comprising: a first gate conductor and a second gate conductor in line with the first gate conductor and upon a first dielectric material; a gate cut region comprising a gate cut dielectric filling the gate cut region and directly upon an end of the first gate conductor and directly upon an end of the second gate conductor, wherein the gate cut dielectric is different from the first dielectric material; a first gate cap upon at least a top surface of the first gate conductor and a second gate cap upon at least a top surface of the second gate conductor; and a gate cut multilayer structure directly upon a top surface of the gate cut dielectric and between the first gate cap and the second gate cap, the gate cut multilayer structure comprising an inner dielectric composed of the first dielectric material between a first high-k dielectric vertical spacer and a second high-k dielectric vertical spacer, wherein a first sidewall of the gate cut multilayer structure is coplanar with the end of the first gate conductor and a second opposing sidewall of the gate cut multilayer structure is coplanar with the end of the second gate conductor, and wherein respective top surfaces of the first gate cap, the second gate cap, and the gate cut multilayer structure are substantially coplanar.
10. 10 . The semiconductor device of claim 9 , wherein a bottom surface of the gate cut multilayer structure is above the top surface of the first gate conductor and is above the top surface of the second gate conductor.
11. 11 . The semiconductor device of claim 9 , wherein the first sidewall of the gate cut multilayer structure is coplanar with an end of the first gate cap and the second opposing sidewall of the gate cut multilayer structure is coplanar with an end of the second gate cap.
12. 12 . The semiconductor device of claim 9 , further comprising: a third gate conductor between a lower gate spacer and an upper gate spacer.
13. 13 . The semiconductor device of claim 12 , wherein a bottom surface of the gate cut multilayer structure is coplanar with a bottom surface of the upper gate spacer.
14. 14 . The semiconductor device of claim 12 , wherein a bottom surface of the gate cut multilayer structure is coplanar with a top surface of the lower gate spacer.
15. 15 . The semiconductor device of claim 12 , wherein a horizontal thickness of the first high-k dielectric spacer is the same as a horizontal thickness of the second high-k dielectric spacer and is the same as a horizontal thickness of the upper gate spacer.
16. 16 . A semiconductor device comprising: a first gate conductor and a second gate conductor in line with the first gate conductor and upon a first dielectric material; a gate cut region comprising a gate cut dielectric filling the gate cut region and directly upon an end of the first gate conductor and directly upon an end of the second gate conductor, wherein the gate cut dielectric is different from the first dielectric material; and a gate cut multilayer structure directly upon a top surface of the gate cut dielectric, the gate cut multilayer structure comprising an inner dielectric composed of the first dielectric material between a first high-k dielectric vertical spacer and a second high-k dielectric vertical spacer, wherein a first sidewall of the gate cut multilayer structure is coplanar with the end of the first gate conductor and a second opposing sidewall of the gate cut multilayer structure is coplanar with the end of the second gate conductor.
17. 17 . The semiconductor device of claim 16 , wherein a top surface of the gate cut multilayer structure is above respective top surfaces of the first gate conductor and the second gate conductor.
18. 18 . The semiconductor device of claim 16 , wherein a bottom surface of the gate cut multilayer structure is above a top surface of the first gate conductor and is above a top surface of the second gate conductor.
19. 19 . The semiconductor device of claim 16 , further comprising: a first gate cap upon at least a top surface of the first gate conductor and a second gate cap upon at least a top surface of the second gate conductor.
20. 20 . The semiconductor device of claim 19 , wherein the first gate cap, the second gate cap, and the gate cut dielectric are respectively composed of a same dielectric material.

Description

BACKGROUND Various embodiments of the present application generally relate semiconductor device fabrication methods and resulting structures. More specifically the various embodiments relate to a semiconductor device that includes a gate cut region that is fabricated after fabrication of an associated replacement gate. SUMMARY In an embodiment of the present invention, a semiconductor device is presented. The semiconductor device includes a first replacement gate upon a semiconductor substrate. The semiconductor device further includes a gate cut region that separates the first replacement gate into a first gate and a second gate. The semiconductor device further includes a gate cut dielectric within the gate cut region. The semiconductor device further includes a first gate cap upon a top surface of the first gate and a second gate cap upon a top surface of the second gate. The semiconductor device further includes a gate cut multilayer structure between the first gate cap and the second gate cap. The gate cut multilayer structure includes a dielectric between a first spacer and a second spacer. A first sidewall of the multilayer structure is coplanar with an end of the first gate and a second opposing sidewall of the multilayer structure is coplanar with an end of the second gate. In an embodiment of the present invention, another semiconductor device is presented. The semiconductor device includes a first gate upon a semiconductor substrate and a second gate upon the semiconductor substrate in line with the first gate. The semiconductor device further includes a gate cut dielectric between the first gate and the second gate. The semiconductor device further includes a first gate cap upon a top surface of the first gate and a second gate cap upon a top surface of the second gate. The semiconductor device further includes a gate cut multilayer structure between the first gate cap and the second gate cap. The gate cut multilayer structure includes a dielectric between a first vertical spacer and a second vertical spacer. A first sidewall of the multilayer structure is coplanar with an end of the first gate and a second opposing sidewall of the multilayer structure is coplanar with an end of the second gate. In another embodiment of the present invention, a semiconductor device fabrication method is presented. The method includes forming a first gate upon a semiconductor substrate and forming a second gate upon the semiconductor substrate in line with the first gate. The method further includes forming a gate cut dielectric between the first gate and the second gate. The method further includes forming a first gate cap upon a top surface of the first gate and forming a second gate cap upon a top surface of the second gate. The method further includes forming a gate cut multilayer structure between the first gate cap and the second gate cap. The gate cut multilayer structure includes a dielectric between a first vertical spacer and a second vertical spacer. A first sidewall of the multilayer structure is coplanar with an end of the first gate and a second opposing sidewall of the multilayer structure is coplanar with an end of the second gate. These and other embodiments, features, aspects, and advantages will become better understood with reference to the following description, appended claims, and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 defines various cross-sectional views of one or more semiconductor devices, in accordance with one or more embodiments. FIG. 2 through FIG. 15 depicts cross-sectional views of a semiconductor device shown after one or more fabrication operations, in accordance with one or more embodiments. FIG. 16 through FIG. 24 depicts cross-sectional views of a semiconductor device shown after one or more fabrication operations, in accordance with one or more embodiments. FIG. 25 is a flow diagram illustrating a semiconductor device fabrication method, in accordance with one or more embodiments. FIG. 26 is a flow diagram illustrating a semiconductor device fabrication method, in accordance with one or more embodiments. DETAILED DESCRIPTION It is understood in advance that although a detailed description is provided herein of an exemplary field effect transistor (FET) architecture that includes a gate cut region that is fabricated after fabrication of an associated replacement gate, implementation of the teachings recited herein are not limited to the particular FET architecture described herein. Rather, embodiments of the present invention are capable of being implemented in conjunction with any other appropriate type of FET device now known or later developed. Various embodiments of the present invention are described herein with reference to the related drawings. Alternative embodiments can be devised without departing from the scope of this invention. It is noted that various connections and positional relationships (e.g., over, below, adjacent, etc.) are set fo