US-12622038-B2 - MV device and method for manufacturing same

US12622038B2US 12622038 B2US12622038 B2US 12622038B2US-12622038-B2

Abstract

An MV device is disclosed. A gate conductive material layer is segmented into a body gate conductive material layer and two edge gate conductive material layers along a channel length direction. The two edge gate conductive material layers are located on two sides of the body gate conductive material layer and are spaced apart from the body gate conductive material layer by dielectric segmentation structures. The lightly doped drain regions extend under the first side face and the second side face of the gate conductive material layer, to reach under the body gate conductive material layer, such that the channel region becomes located under the body gate conductive material layer; and the edge gate conductive material layers and the dielectric segmentation structures become located above the lightly doped drain regions. The present disclosure also discloses a method for manufacturing an MV device.

Inventors

Qiwei Wang
Tao Liu
Haoyu Chen

Assignees

Shanghai Huali Integrated Circuit Corporation

Dates

Publication Date: 20260505
Application Date: 20230828
Priority Date: 20220916

Claims (8)

1 . A method for manufacturing a medium voltage (MV) device, comprising: step 1 , providing a semiconductor substrate, forming two lightly doped drain regions in selected regions of the semiconductor substrate; forming a channel region in a surface of the semiconductor substrate between the two lightly doped drain regions; step 2 , forming a gate dielectric layer on the surface of the semiconductor substrate; step 3 , growing a gate conductive material layer on a surface of the gate dielectric layer; performing a first patterning on the gate conductive material layer to form side faces on the gate conductive material layer and a segmentation trench on each side; and dividing the gate conductive material layer into a body gate conductive material layer and two edge gate conductive material layers along a channel length direction, wherein the body gate conductive material layer is located in a middle region, the two edge gate conductive material layers are located on two sides of the body gate conductive material layer, and wherein the two edge gate conductive material layers each is spaced apart from the body gate conductive material layer by the segmentation trench; wherein a first side face and a second side face of the gate conductive material layer are outer surfaces of the edge gate conductive material layers and located along the channel length direction; wherein the lightly doped drain regions extend under the first side face and the second side face of the gate conductive material layer, to reach under the body gate conductive material layer, such that the channel region becomes located under the body gate conductive material layer; and wherein the edge gate conductive material layers become located above the lightly doped drain regions; step 4 , forming spacers on side faces of the gate conductive material layer; step 5 , filling each segmentation trench with a dielectric segmentation structure, wherein forming the dielectric segmentation structure comprises forming a first dielectric layer of the spacers, wherein the first dielectric layer does not fully fill the segmentation trench and leaves a gap in the segmentation trench; and forming a second dielectric layer to fill the gap of the segmentation trench; wherein the first dielectric layer and the second dielectric layer are stacked in the segmentation trench; and step 6 , forming source drain implantation regions in a self-aligned process on surfaces of the lightly doped drain regions outside the spacers away from the first side face and the second side face of the gate conductive material layer.
2 . The method for manufacturing the MV device according to claim 1 , wherein, in step 5 , the first dielectric layer is made in a same process as the spacers are made in step 4 .
3 . The method for manufacturing the MV device according to claim 2 , wherein a width of the segmentation trench is less than or equal to twice a thickness of a bottom of the spacer, and wherein the first dielectric layer fills the segmentation trench to form the dielectric segmentation structure, and wherein step 4 and step 5 are implemented together.
4 . The method for manufacturing the MV device according to claim 2 , wherein a width of the segmentation trench is greater than twice a thickness of a bottom of the spacer.
5 . The method for manufacturing the MV device according to claim 1 , wherein the forming the second dielectric layer in step 5 is implemented after step 6 , and wherein the method further comprises fully filling the gap of the segmentation trench with a photoresist before step 6 , and then performing step 6 , followed by removing the photoresist from the segmentation trench.
6 . The method for manufacturing the MV device according to claim 1 , wherein the first dielectric layer comprises an oxide layer, or a nitride layer, or a stack layer of an oxide layer and a nitride layer; and wherein the second dielectric layer comprises an oxide layer, or a nitride layer, or a stack layer of an oxide layer and a nitride layer.
7 . The method for manufacturing the MV device according to claim 1 , wherein a material of the gate dielectric layer comprises an oxide layer.
8 . The method for manufacturing the MV device according to claim 1 , wherein a material of the gate conductive material layer comprises polysilicon.

Description

CROSS-REFERENCES TO RELATED APPLICATIONS This application claims the priority to Chinese patent application No. 202211129333.5, filed on Sep. 16, 2022, and entitled “MV DEVICE AND METHOD FOR MANUFACTURING SAME”, the disclosure of which is incorporated herein by reference in entirety. TECHNICAL FIELD The present disclosure relates to the field of semiconductor integrated circuit manufacturing, in particular to a medium voltage (MV) device. The present disclosure also relates to a method for manufacturing an MV device. BACKGROUND The high voltage (HV) IC device manufacturing process at the 28 nm note platform includes inserting medium and high voltage devices, i.e., a medium voltage device and a high voltage device, on a 28 nm HK platform. After inserting the medium and high voltage devices, a low voltage (LV) device, a medium voltage device, and a high voltage device are integrated together on the same semiconductor substrate. For example, a core device or SRAM device includes the LV device, and an input output (IO) device includes the medium voltage device. A working voltage of the LV device reaches a few tenths of a volt or one plus a few tenths of a volt, a working voltage of the medium voltage device reaches several volts, such as 8V, and a working voltage of the high voltage device is higher. The provision of a field oxide is typically required in a drift region of the high voltage device. In an integrated process, the medium voltage device and the core/SRAM device share the same gate spacer, for example, an 8V MV and a 0.9V core/SRAM share the same spacer. Due to hard constraints of a pitch of the SRAM, the gate spacer cannot be too thick. In the present application, the thickness of the spacer refers to a lateral width of the gate spacer. As the result, a gate induced drain leakage (GIDL) in the MV device is severe. Currently, in the industry, ways to improve the GIDL are mainly by adjusting a lightly doped drain (LDD) region of the MV device, but the improvement is limited with a very small process window. FIGS. 1A-1D are schematic diagrams of cross sectional structures in various steps of an existing method for manufacturing an MV device. The existing method for manufacturing an MV device includes the following steps: Step 1. Referring to FIG. 1A, a semiconductor substrate 101 is provided, wherein two lightly doped drain regions 102 are formed in selected regions of the semiconductor substrate 101. A channel region 103 is located in a surface region of the semiconductor substrate 101 between the two lightly doped drain regions 102. Typically, a field oxide layer such as a shallow trench isolation (STI) is also formed on the semiconductor substrate 101. The field oxide layer isolates an active region, that is, a region of the semiconductor substrate 101 surrounded by the field oxide layer forms the active region. A formation region of the MV device is located in a first active region 101a, and the first active region 101a is composed of the semiconductor substrate 101 in the region surrounded by the field oxide layer. Typically, an HV device and an LV device are integrated simultaneously on the semiconductor substrate 101, and formation regions of the HV device and the LV device are located in respective active regions. Step 2. Referring to 1A, a gate dielectric layer 104 is formed on a surface of the semiconductor substrate 101. The grown gate dielectric layer 104 covers the entire surface of the semiconductor substrate 101. Typically, after the growth of the gate dielectric layer 104, a patterned etching process is required to retain the gate dielectric layer 104 in only the first active region 101a. The gate dielectric layer 104 in the formation regions of the HV device and the LV device needs to be removed. Formation processes of the HV device and LV device are not described in detail in the description of the present application. Step 3. Referring to FIG. 1A, a gate conductive material layer 105 is grown. A first patterned etching is performed to form on the gate conductive material layer 105, and the first patterned etching forms all side faces of the gate conductive material layer 105. The gate conductive material layer 105 is located in only a formation region of a gate structure after the first patterned etching. A first side face and a second side face of the gate conductive material layer 105 are two side faces located in a channel length direction. A third side face and a fourth side face of the gate conductive material layer 105 are two side faces located in a channel width direction. In FIG. 2, the channel length direction corresponds to a horizontal direction in a plane shown in FIG. 2, and the channel width direction corresponds to a vertical direction in the plane shown in FIG. 2. Step 4. Referring to FIG. 1B, a spacer process is performed to form spacers 106 on all the side faces of the gate conductive material layer 105. The spacer process includes deposition of a spacer dielectric