US-12622041-B2 - Gate dielectric for gate leakage reduction

Abstract

Gate stack fabrication techniques are disclosed for capacitance equivalent thickness scaling. An exemplary method for forming a gate stack includes forming an interfacial layer, forming a high-k dielectric layer over the interfacial layer, and forming an electrically conductive gate layer over the high-k dielectric layer. Forming the high-k dielectric layer includes forming a group 4 element-containing dielectric layer (e.g., an HfO 2 layer and/or a ZrO 2 layer) and forming a rare earth element-containing dielectric layer. In some embodiments, the rare earth element-containing dielectric layer includes yttrium and oxygen, nitrogen, carbon, or a combination thereof. The electrically conductive gate layer is formed over the rare earth element-containing dielectric layer (i.e., the rare earth element-containing dielectric layer is not removed and remains in the gate stack). The rare earth element-containing dielectric layer can be formed before, after, or between forming sublayers of group 4 element-containing dielectric layer.

Inventors

• Shen-Yang LEE
• Hsiang-Pi Chang
• HUANG-LIN CHAO
• Pinyen Lin

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date

20260505

Application Date

20230602

Claims (20)

1. 1 . A method for forming a gate stack, the method comprising: forming an interfacial layer; forming a high-k dielectric layer over the interfacial layer, wherein the forming the high-k dielectric layer includes: forming a group 4 element-containing dielectric layer, and forming a rare earth element-containing dielectric layer; and forming an electrically conductive gate layer over the rare earth element-containing dielectric layer, wherein the forming the group 4 element-containing dielectric layer includes: forming a first sublayer of the group 4 element-containing dielectric layer before forming the rare earth element-containing dielectric layer, and forming a second sublayer of the group 4 element-containing dielectric layer after forming the rare earth element-containing dielectric layer, such that the rare earth element-containing dielectric layer is disposed between the first sublayer of the group 4 element-containing dielectric layer and the second sublayer of the group 4 element-containing dielectric layer and the electrically conductive gate layer is formed on the second sublayer of the group 4 element-containing dielectric layer.
2. 2 . The method of claim 1 , further comprising performing a thermal treatment before forming the electrically conductive gate layer.
3. 3 . The method of claim 2 , further comprising forming a sacrificial cap over the high-k dielectric layer before performing the thermal treatment and removing the sacrificial cap after performing the thermal treatment.
4. 4 . The method of claim 1 , further comprising performing a thermal treatment after forming the rare earth element-containing dielectric layer and before forming the second sublayer of the group 4 element-containing dielectric layer.
5. 5 . The method of claim 1 , wherein: the forming the group 4 element-containing dielectric layer includes performing atomic layer deposition to form a hafnium-based oxide layer or a zirconium-based oxide layer; and the forming the rare earth element-containing dielectric layer includes performing atomic layer deposition to form a yttrium-based oxide layer.
6. 6 . The method of claim 1 , further comprising forming a dipole dopant source layer over the group 4 element-containing dielectric layer, performing a thermal drive-in process to drive dipole dopant from the dipole dopant source layer into the group 4 element-containing dielectric layer, and removing the dipole dopant source layer.
7. 7 . The method of claim 6 , further comprising forming the dipole dopant source layer over the first sublayer of the group 4 element-containing dielectric layer and removing the dipole dopant source layer before forming the rare earth element-containing dielectric layer.
8. 8 . The method of claim 1 , wherein a thickness of the rare earth element-containing dielectric layer is about 1% to about 50% of a thickness of the high-k dielectric layer.
9. 9 . A method comprising: forming a channel layer; forming a gate dielectric on the channel layer, wherein the gate dielectric includes a first dielectric layer and a second dielectric layer, the second dielectric layer is over the first dielectric layer, the second dielectric layer includes a group 4 element and a rare earth element, and the second dielectric layer includes a rare earth element band where an atomic concentration of the rare earth element is greater than an atomic concentration of the group 4 element; forming a gate electrode over the gate dielectric; and wherein the forming the gate dielectric includes: depositing a first oxide layer over the channel layer, wherein the first oxide layer forms the first dielectric layer of the gate dielectric, depositing a second oxide layer over the first oxide layer, wherein the second oxide layer includes the group 4 element, depositing a third oxide layer over the first oxide layer, wherein the third oxide layer includes the rare earth element, and further wherein the second oxide layer and the third oxide layer form the second dielectric layer, and performing a thermal treatment before forming the gate electrode, wherein the thermal treatment is an annealing process performed after depositing a sacrificial cap over the second oxide layer, wherein the sacrificial cap is removed after the annealing process.
10. 10 . The method of claim 9 , wherein the forming the gate dielectric further includes depositing a fourth oxide layer over the third oxide layer, wherein the fourth oxide layer includes the group 4 element and the fourth oxide layer forms the second dielectric layer.
11. 11 . The method of claim 10 , wherein the thermal treatment is performed after depositing the fourth oxide layer.
12. 12 . The method of claim 9 , wherein: the depositing the second oxide layer includes depositing a hafnium oxide layer; and the depositing the third oxide layer includes depositing an yttrium oxide layer.
13. 13 . The method of claim 9 , wherein the forming the gate dielectric further includes performing dipole engineering on the second oxide layer.
14. 14 . The method of claim 9 , further comprising depositing the sacrificial cap over the third oxide layer.
15. 15 . The method of claim 9 , wherein a thickness of the third oxide layer is about 1% to about 50% of a sum of a thickness of the second oxide layer and the third oxide layer.
16. 16 . The method of claim 9 , wherein: the group 4 element is hafnium (Hf), zirconium (Zr), or a combination thereof; and the rare earth element is yttrium (Y), scandium (Sc), lutetium (Lu), thulium (Tm), gadolinium (Gd), or a combination thereof.
17. 17 . A semiconductor structure comprising: a semiconductor channel, a first source/drain, and a second source/drain, wherein the semiconductor channel extends between the first source/drain and the second source/drain; and a gate stack disposed on the semiconductor channel, wherein the gate stack includes: a gate dielectric on the semiconductor channel, wherein: the gate dielectric includes a high-k dielectric layer over an interfacial layer, wherein the high-k dielectric layer includes a group 4 element, a rare earth element, and oxygen; and the high-k dielectric layer has a rare earth element band where an atomic concentration of the rare earth element is greater than an atomic concentration of the group 4 element, and a gate electrode over the gate dielectric.
18. 18 . The semiconductor structure of claim 17 , wherein: the group 4 element is hafnium, zirconium, or a combination thereof; and the rare earth element is yttrium.
19. 19 . The semiconductor structure of claim 17 , wherein the high-k dielectric layer includes a group 4 element-containing dielectric layer that includes the group 4 element and oxygen and a rare earth element-containing dielectric layer that includes the rare earth element and oxygen.
20. 20 . The semiconductor structure of claim 17 , wherein a thickness of the rare earth element band is about 1% to about 50% of a total thickness of the high-k dielectric layer.

Description

This is a non-provisional application of and claims benefit of U.S. Provisional Patent Application Ser. No. 63/483,654, filed Feb. 7, 2023, the entire disclosure of which is incorporated herein by reference. BACKGROUND The electronics industry has experienced an ever-increasing demand for smaller and faster electronic devices that are simultaneously able to support a greater number of increasingly complex and sophisticated functions. To meet these demands, there is a continuing trend in the integrated circuit (IC) industry to manufacture low-cost, high-performance, and low-power ICs. Thus far, these goals have been achieved in large part by reducing IC dimensions (for example, minimum IC feature size), thereby improving production efficiency and lowering associated costs. However, such scaling has also increased complexity of the IC manufacturing processes. Thus, realizing continued advances in IC devices and their performance requires similar advances in IC manufacturing processes and technology. One such advancement has been the implementation of high-k/metal gate stacks in metal-oxide-semiconductor field-effect transistors (MOSFETs) as they are scaled down through various IC technology nodes. Capacitance equivalent thickness (CET) scaling of the gate stack's high-k dielectric material, for example, by reducing its thickness, can further improve MOSFET performance. However, as device dimensions shrink, it has been observed that reducing high-k dielectric material thickness can lead to undesired increases in leakage current. Accordingly, although existing high-k/metal gate stacks and methods of manufacturing such high-k/metal gate stacks have been generally adequate for their intended purposes, as device scaling down continues, they have not been entirely satisfactory in all respects. BRIEF DESCRIPTION OF THE DRAWINGS The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 is a flow chart of a method for fabricating a device having a gate stack, in portion or entirety, according to various aspects of the present disclosure. FIG. 2 is a perspective view of a device, such as a transistor, in portion or entirety, at a fabrication stage associated with a method for fabricating a device having a gate stack, such as the method of FIG. 1, according to various aspects of the present disclosure. FIGS. 3A-15A and FIGS. 3B-15B are various views of a device, such as a transistor, in portion or entirety, at various fabrication stages associated with the method of FIG. 1 according to various aspects of the present disclosure. FIG. 16 is a flow chart of another method for fabricating a device having a gate stack, in portion or entirety, according to various aspects of the present disclosure. FIGS. 17A-29A and FIGS. 17B-29B are various views of a device, such as a transistor, in portion or entirety, at various fabrication stages associated with the method of FIG. 16, according to various aspects of the present disclosure. FIG. 30 is a flow chart of another method for fabricating a device having a gate stack, in portion or entirety, according to various aspects of the present disclosure. FIGS. 31A-44A and FIGS. 31B-44B are various views of a device, such as a transistor, in portion or entirety, at various fabrication stages associated with the method of FIG. 30, according to various aspects of the present disclosure. FIG. 45 is a graph that depicts flat-band voltage as a function of capacitance equivalent thickness for transistors having different high-k dielectric layers, such as those described herein, according to various aspects of the present disclosure. FIG. 46 is a graph that depicts leakage current as a function of capacitance equivalent thickness for transistors having different high-k dielectric layers, such as those described herein, according to various aspects of the present disclosure. FIG. 47 illustrates an energy band diagram of a metal-insulator-semiconductor structure, such as a gate electrode-gate dielectric-channel structure, of a transistor according to various aspects of the present disclosure. DETAILED DESCRIPTION The present disclosure relates generally to semiconductor devices, and more particularly, to gate dielectrics and methods of fabrication thereof for transistors. The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in