US-12622042-B2 - Multi-layered or graded gate dielectric in thin film transistor (TFT) structures

US12622042B2US 12622042 B2US12622042 B2US 12622042B2US-12622042-B2

Abstract

Techniques are provided herein for forming thin film transistor structures having a multilayer and/or concentration gradient gate dielectric. Such a gate dielectric can be used, to tune the performance and/or reliability of the transistor. According to some such embodiments, memory structures having thin film transistor (TFT) structures are arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory structure arrays are formed within the interconnect region. Any of the given TFT structures may include a multilayer and/or graded gate dielectric that includes at least two or more different dielectric layers and/or a material concentration gradient through a thickness of the gate dielectric.

Inventors

Abhishek Anil Sharma
Moshe Dolejsi
Vishak Venkatraman
Christopher Ryder
Deepyanti Taneja
Albert B. Chen
Mark Armstrong
Afrin Sultana
Van H. Le
Travis W. LaJoie
Shailesh Kumar Madisetti
Timothy JEN
Cheng Tan

Assignees

INTEL CORPORATION

Dates

Publication Date: 20260505
Application Date: 20220512

Claims (20)

1 . An integrated circuit, comprising: a gate electrode; a first gate dielectric layer on the gate electrode; a second gate dielectric layer on the first gate dielectric layer, wherein the first gate dielectric layer has a lower dielectric constant than the second gate dielectric layer; a semiconductor region over the second gate dielectric layer; one or more dielectric layers over the semiconductor region; and one or more conductive contacts that extend through the one or more dielectric layers and contact a respective portion of the semiconductor region.
2 . The integrated circuit of claim 1 , wherein one of the one or more conductive contacts is coupled to a metal-insulator-metal (MIM) capacitor.
3 . The integrated circuit of claim 1 , wherein the semiconductor region comprises a metal oxide semiconductor material.
4 . The integrated circuit of claim 1 , wherein the first gate dielectric layer is at least 2 nm thinner than the second gate dielectric layer.
5 . The integrated circuit of claim 1 , wherein the first gate dielectric layer comprises oxygen or nitrogen and any of silicon, titanium, or boron.
6 . The integrated circuit of claim 1 , wherein the second gate dielectric layer comprises oxygen and one of hafnium, zirconium, aluminum or lanthanum.
7 . The integrated circuit of claim 1 , wherein one or both of the first gate dielectric layer and the second gate dielectric layer includes an element with a graded concentration through a thickness of the one or both of the first gate dielectric layer and the second gate dielectric layer.
8 . A printed circuit board comprising the integrated circuit of claim 1 .
9 . An integrated circuit, comprising: a plurality of semiconductor devices; an interconnect region above the plurality of semiconductor devices, the interconnect region comprising a plurality of stacked interconnect layers; and a thin film transistor (TFT) structure across one or more interconnect layers of the plurality of stacked interconnect layers, the TFT structure comprising a gate electrode, a first gate dielectric layer on the gate electrode, a second gate dielectric layer on the first gate dielectric layer, a semiconductor region over the second gate dielectric layer, one or more dielectric layers over the semiconductor region, and one or more conductive contacts that extend through the one or more dielectric layers and contact a respective portion of the semiconductor region.
10 . The integrated circuit of claim 9 , wherein one of the one or more conductive contacts is coupled to a metal-insulator-metal (MIM) capacitor.
11 . The integrated circuit of claim 9 , wherein the first gate dielectric layer has a thickness between about 0.5 nm and about 3 nm, and the second gate dielectric layer has a thickness between about 1 nm and about 50 nm.
12 . The integrated circuit of claim 9 , wherein the first gate dielectric layer has a lower dielectric constant than the second gate dielectric layer.
13 . The integrated circuit of claim 9 , wherein the first gate dielectric layer comprises oxygen or nitrogen and any of silicon, titanium, or boron.
14 . The integrated circuit of claim 9 , wherein the second gate dielectric layer comprises oxygen and one of hafnium, zirconium, aluminum or lanthanum.
15 . The integrated circuit of claim 9 , wherein the TFT structure is a first TFT structure of an array of TFT structures across the one or more interconnect layers.
16 . An integrated circuit, comprising: a plurality of semiconductor devices; an interconnect region above the plurality of semiconductor devices, the interconnect region comprising a plurality of stacked interconnect layers; and a thin film transistor (TFT) structure across one or more interconnect layers of the plurality of stacked interconnect layers, the TFT structure comprising a gate electrode, a gate dielectric layer on the gate electrode, a semiconductor region on the gate dielectric layer, one or more dielectric layers over the semiconductor region, and one or more conductive contacts that extend through the one or more dielectric layers and contact a respective portion of the semiconductor region; wherein the gate dielectric layer has a graded material composition such that a given element has a first concentration at a first surface of the gate dielectric layer contacting the gate electrode and a second concentration different from the first concentration at a second surface of the gate dielectric layer contacting the semiconductor region.
17 . The integrated circuit of claim 16 , wherein one of the one or more conductive contacts is coupled to a metal-insulator-metal (MIM) capacitor.
18 . The integrated circuit of claim 16 , wherein the gate dielectric layer comprises oxygen and the given element is one of hafnium, zirconium, aluminum or lanthanum.
19 . The integrated circuit of claim 18 , wherein the second concentration is greater than the first concentration.
20 . The integrated circuit of claim 16 , wherein the TFT structure is a first TFT structure of an array of TFT structures across the one or more interconnect layers.

Description

FIELD OF THE DISCLOSURE The present disclosure relates to integrated circuits, and more particularly, to multilayer and/or or concentration gradient gate dielectrics in thin film transistor structures. BACKGROUND As integrated circuits continue to scale downward in size, a number of challenges arise. For instance, as transistor area decreases, so too do the dimensions for interconnects made to the various transistor structures, such as gate structures, drain regions, and source regions. Structures formed in such interconnect layers may be highly affected by process variations leading to subsequent variations in device performance or low yield of workable devices. Accordingly, there remain a number of non-trivial challenges with respect to the formation of backend structures in integrated circuits. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a cross-sectional view that illustrates an example portion of an integrated circuit configured with an interconnect region having tiers of memory structures that include thin film transistor structures having a multilayer or graded gate dielectric, in accordance with an embodiment of the present disclosure. FIG. 1B is a plan view of an array of memory structures and generally illustrates structures formed across different interconnect layers, in accordance with an embodiment of the present disclosure. FIGS. 2A-2J′ are cross-sectional views that collectively illustrate an example process for forming a thin film transistor (TFT) based memory structure having a multi-layer and/or concentration gradient gate dielectric, in accordance with an embodiment of the present disclosure. FIG. 3 illustrates a cross-section view of a chip package containing one or more semiconductor dies, in accordance with some embodiments of the present disclosure. FIG. 4 is a flowchart of a method for forming a TFT structure having a multi-layer and/or concentration gradient gate dielectric, in accordance with an embodiment of the present disclosure. FIG. 5 illustrates a computing system including one or more integrated circuits, as variously described herein, in accordance with an embodiment of the present disclosure. Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent in light of this disclosure. As will be further appreciated, the figures are not necessarily drawn to scale or intended to limit the present disclosure to the specific configurations shown. For instance, while some figures generally indicate perfectly straight lines, right angles, and smooth surfaces, an actual implementation of an integrated circuit structure may have less than perfect straight lines, right angles (e.g., some features may have tapered sidewalls and/or rounded corners), and some features may have surface topology or otherwise be non-smooth, given real world limitations of the processing equipment and techniques used. DETAILED DESCRIPTION Techniques are provided herein for forming thin film transistor structures having a multilayer and/or concentration gradient gate dielectric. While the techniques can be used in any number of applications, they are particularly useful in forming backend (e.g., within the interconnect region) memory structures configured with TFTs having a multi-layer and/or concentration gradient gate dielectric (e.g., dielectric layers between a gate electrode and a semiconductor region). Such a gate dielectric can be used, to tune the performance and/or reliability of the transistor. For example, the different layers (or concentration gradient(s) within a given layer, as the case may be, can be selected to reduce source/drain current leakage while maintaining interfaces between the gate dielectric and each of the gate electrode and semiconductor region that have a low number of charge traps (e.g., minimal number of dangling bonds and low stress). According to an example, a given memory structure generally includes memory cells, with each memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT) structure, and the storage device may include a capacitor. In such cases, the TFT structure allows the capacitor to be accessed during write operations (to store a memory bit) and read operations (to read a previously-stored bit). According to some such embodiments, the memory structures are arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory structure arrays are formed within the interconnect region. Any of the given TFT structures may include a multilayer and/or graded gate dielectric that includes at least two or more different dielectric layers and/or a material concentration gradient through a thickness of the gate dielectric. Numerous variations and embodiments will be apparent in light of this disclosure.