US-12622043-B2 - Gate etch back with reduced loading effect

Abstract

A semiconductor device includes first and second gate structures over a substrate, the first gate structure has a first width that is smaller than a second width of the second gate structure, in which a lower portion of the first gate structure having a first work-function material (WFM) layer, the first WFM layer having a top surface, a lower portion of the second gate structure having a second WFM layer, the second WFM layer having a top surface. A first gate electrode is disposed over the first WFM layer and a second gate electrode has a lower portion disposed in the second WFM layer, in which the first gate electrode has a first width that is smaller than a second width of the second gate electrode, and wherein the top surface of the second WFM layer is at a level below a top surface of the second gate electrode.

Inventors

• Yi-Chen Lo
• Jung-Hao CHANG
• Li-Te Lin
• Pinyen Lin

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Dates

Publication Date

20260505

Application Date

20231103

Claims (20)

1. 1 . A method, comprising: forming a first gate structure and a second gate structure over a substrate, the second gate structure being wider than the first gate structure; etching back the first gate structure and the second gate structure; performing a deposition process to form a sacrificial layer spanning over the first gate structure and the second gate structure, wherein the deposition process comprises employing a chlorine-containing gas in a hydrogen-containing environment; performing an etching back process to the sacrificial layer to expose top surfaces of the first gate structure and the second gate structure, while leaving remaining portions of the sacrificial layer on sidewalls of the first gate structure and the second gate structure; and performing an etching process to etch the sacrificial layer, the first gate structure, and the second gate structure, wherein the etching process comprises employing the chlorine-containing gas in a hydrogen-free environment.
2. 2 . The method of claim 1 , wherein the etching back is also performed in a hydrogen-free environment.
3. 3 . The method of claim 1 , wherein the remaining portions of the sacrificial layer are in contact with sidewalls of gate metals of the first and second gate structures.
4. 4 . The method of claim 1 , wherein the etching back process is performed such that a top end of a first work function metal layer of the first gate structure is lower than a top end of a second work function metal layer of the second gate structure.
5. 5 . The method of claim 1 , further comprising removing the sacrificial layer from the first and second gate structures after performing the etching process.
6. 6 . The method of claim 5 , further comprising thinning down the first and second gate structures after removing the sacrificial layer.
7. 7 . The method of claim 6 , further comprising forming a dielectric cap layer covering the first and second gate structures after thinning down the first and second gate structures.
8. 8 . A method, comprising: forming a first gate structure and a second gate structure over a substrate, the second gate structure being wider than the first gate structure, wherein each of the first gate structure and the second gate structure comprises a gate dielectric layer, a work function metal layer over the gate dielectric layer, and a filling metal over the work function metal layer; etching back the first gate structure and the second gate structure; performing a deposition process to form a sacrificial layer over the first gate structure and the second gate structure, wherein the sacrificial layer interfaces a top end of the gate dielectric layer of each of the first gate structure and the second gate structure, wherein the deposition process comprises employing a chlorine-containing gas in a hydrogen-containing environment, and wherein the deposition process comprises a plurality of deposition cycles, wherein each of the deposition cycle comprises: performing a first plasma treatment to form a material of the sacrificial layer; and performing a second plasma treatment to thin down the material of the sacrificial layer; and performing an etching process to etch the sacrificial layer, the first gate structure, and the second gate structure, wherein the etching process comprises employing the chlorine-containing gas in a hydrogen-free environment.
9. 9 . The method of claim 8 , wherein etching back the first gate structure and the second gate structure is performed such that the top end of the gate dielectric layer and a top end of the work function metal layer are lower than a top end of the gate metal.
10. 10 . The method of claim 8 , wherein the material of the sacrificial layer comprises BCl x compound.
11. 11 . The method of claim 8 , wherein the first plasma treatment is performed using BCl 3 gas, H 2 gas, and Ar gas, while the second plasma treatment is performed using Ar gas without using BCl 3 gas and H 2 gas.
12. 12 . The method of claim 8 , wherein the first plasma treatment is performed in a hydrogen-containing environment, while the second plasma treatment is performed in a hydrogen-free environment.
13. 13 . The method of claim 8 , wherein the first plasma treatment and the second plasma treatment are performed in-situ.
14. 14 . The method of claim 8 , wherein etching back the first gate structure and the second gate structure and the deposition process are performed in-situ.
15. 15 . A method, comprising: forming a first gate structure and a second gate structure over a substrate, the second gate structure being wider than the first gate structure, wherein each of the first gate structure and the second gate structure comprises a filling metal and a work function metal layer lining the filling metal; etching back the first gate structure and the second gate structure; performing a deposition process to form a sacrificial layer over the first gate structure and the second gate structure, wherein the deposition process comprises employing a chlorine-containing gas in a hydrogen-containing environment, and wherein etching back the first gate structure and the second gate structure and the deposition are performed in a same chamber; and performing an etching process to etch the sacrificial layer, the first gate structure, and the second gate structure, wherein the etching process comprises employing the chlorine-containing gas in a hydrogen-free environment, and wherein after the etching process is complete, a top surface of the filling metal of the second gate structure comprises a convex portion.
16. 16 . The method of claim 15 , wherein performing the etching process is also performed in the same chamber.
17. 17 . The method of claim 15 , wherein etching back the first gate structure and the second gate structure is performed without using hydrogen gas.
18. 18 . The method of claim 17 , wherein the chlorine-containing gas comprises BCl 3 .
19. 19 . The method of claim 15 , wherein the deposition process comprises a plurality of deposition cycles, wherein each of the deposition cycles comprises a deposition step followed by a thin-down step.
20. 20 . The method of claim 19 , wherein the deposition step is performed using BCl 3 gas, H 2 gas, and Ar gas, while the thin-down step is performed using Ar gas without using BCl 3 gas and H 2 gas.

Description

PRIORITY CLAIM AND CROSS-REFERENCE The present application is a Continuation application of U.S. application Ser. No. 17/856,892, filed on Jul. 1, 2022, which is a Continuation application of U.S. application Ser. No. 17/207,425, filed on Mar. 19, 2021, now U.S. Pat. No. 11,522,065, issued on Dec. 6, 2022, which is a Divisional application of U.S. application Ser. No. 16/158,141, filed on Oct. 11, 2018, now U.S. Pat. No. 10,957,779, issued on Mar. 23, 2021, which claims priority to U.S. Provisional Application Ser. No. 62/592,801, filed Nov. 30, 2017, which are herein incorporated by references. BACKGROUND As the semiconductor industry has strived for higher device density, higher performance, and lower costs, problems involving both fabrication and design have been encountered. One solution to these problems has been the development of a fin-like field effect transistor (FinFET). A FinFET includes a thin vertical ‘fin’ formed in a free standing manner over a major surface of a substrate. The source, drain, and channel regions are defined within this fin. The transistor's gate wraps around the channel region of the fin. This configuration allows the gate to induce current flow in the channel from three sides. Thus, FinFET devices have the benefit of higher current flow and reduced short-channel effects. The dimensions of FinFETs and other metal oxide semiconductor field effect transistors (MOSFETs) have been progressively reduced as technological advances have been made in integrated circuit materials. For example, high-k metal gate (HKMG) processes have been applied to FinFETs. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIGS. 1A to 1B illustrate a block diagram of a method of forming a semiconductor device in accordance with some embodiments. FIGS. 2-15 are perspective views of a wafer W at various stages of the method in FIGS. 1A to 1B. FIGS. 16-23 are cross-sectional views of a semiconductor device at various stages of the method in FIGS. 1A to 1B. FIG. 24 is a cross-sectional view of a plasma chamber in accordance with some embodiments of the present disclosure. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Embodiments of the present disclosure provide an improved metal gate etch back (MGEB) process, which may be employed in any of a variety of device types. For example, embodiments of the present disclosure may be used to form gate stacks suitable for use in planar bulk metal-oxide-semiconductor field-effect transistors (MOSFETs), multi-gate transistors (planar or vertical) such as FinFET devices, gate-all-around (GAA) devices, Omega-gate (Ω-gate) devices, or Pi-gate (Π-gate) devices, as well as strained-semiconductor devices, silicon-on-insulator (SOI) devices, partially-depleted SOI devices, fully-depleted SOI devices, or the like. In addition, embodiments disclosed herein may be employed in the formation of P-type and/or N-type devices. Referring now to FIGS. 1A and 1B, illustrated are an exemplary method M for fabrication of a semiconductor device in accordance with some embodiments, wherein the fabrication i