US-12622044-B2 - Method of making breakdown resistant semiconductor device

Abstract

A method of manufacturing a semiconductor device includes implanting a channel region of a first transistor and a channel region of a second transistor to have a first conductivity type. The method further includes forming source/drain regions of the first transistor to have the first conductivity type and source/drain regions of the second transistor to have a second conductivity type, wherein the second conductivity is different from the first conductivity type. The method further includes depositing a first work function layer over the channel region of the first transistor. The method further includes depositing a second work function layer over the channel region of the second transistor, wherein the first work function layer includes a same material as the second work function layer.

Inventors

• Jhong-Sheng WANG
• Ting-Sheng Huang
• Jiaw-Ren Shih

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date

20260505

Application Date

20200203

Claims (20)

1. 1 . A method of manufacturing a semiconductor device, comprising: implanting both an entirety of a channel region of a first transistor and an entirety of a channel region of a second transistor to have a first conductivity type; forming source/drain regions of the first transistor to have the first conductivity type and source/drain regions of the second transistor to have a second conductivity type, wherein the second conductivity type is different from the first conductivity type, and the channel region of the first transistor is an entire area between the source/drain regions of the first transistor configured to permit current flow in response to a gate of the first transistor receiving a threshold voltage, wherein a depth of the channel region is equal to or greater than a depth of the source/drain regions; forming a well having the second conductivity type, wherein the channel region is between a bottommost surface of the source/drain regions of the first transistor and the well; depositing a first work function layer over the channel region of the first transistor; and depositing a second work function layer over the channel region of the second transistor, wherein the first work function layer includes a same material as the second work function layer.
2. 2 . The method of claim 1 , further comprising: forming a lightly doped drain (LDD) region having the second conductivity type in the second transistor.
3. 3 . The method of claim 1 , wherein implanting the channel region of the first transistor and the channel region of the second transistor comprises: implanting the channel region of the first transistor and the channel region of the second transistor using a same dopant.
4. 4 . The method of claim 1 , wherein implanting the channel region of the first transistor and the channel region of the second transistor comprises: implanting the channel region of the first transistor and the channel region of the second transistor simultaneously.
5. 5 . The method of claim 1 , wherein implanting the channel region of the first transistor and the channel region of the second transistor comprises using a p-type dopant.
6. 6 . The method of claim 1 , wherein implanting the channel region of the first transistor and the channel region of the second transistor comprises using an n-type dopant.
7. 7 . The method of claim 1 , wherein implanting the channel region of the first transistor comprises implanting the channel region of a metal-oxide-semiconductor (MOS) transistor.
8. 8 . The method of claim 1 , wherein implanting the channel region of the first transistor comprises implanting the channel region of a fin field effect transistor (FinFET).
9. 9 . The method of claim 1 , wherein implanting the channel region of the first transistor comprises implanting the channel region of a nanowire field effect transistor (NWFET).
10. 10 . A method of manufacturing a semiconductor device, comprising: doping an entirety of a first channel region of a first transistor with a first dopant having a first conductivity type, wherein doping the first channel region comprises doping the first channel region of a nanowire field effect transistor (NWFET); doping an entirety of a second channel region of a second transistor with a second dopant having the first conductivity type; forming first source/drain regions of the first transistor to have the first conductivity type, and the channel region of the first transistor is an entire area between the first source/drain regions configured to permit current flow in response to a gate of the first transistor receiving a threshold voltage, wherein a depth of the first channel region is equal to or greater than a depth of the first source/drain regions; forming second source/drain regions of the second transistor to have a second conductivity type, wherein the second conductivity is different from the first conductivity type; forming a well having the second conductivity type, wherein the first channel region is between a bottommost surface of the first source/drain regions and the well; forming a first gate electrode over the first channel region, wherein the first gate electrode comprises a first material; and forming a second gate electrode over the second channel region, wherein the second gate electrode comprises the first material.
11. 11 . The method of claim 10 , wherein doping the first channel region comprises doping the first channel region with the first dopant being a same material as the second dopant.
12. 12 . The method of claim 10 , wherein forming the first source/drain regions comprises in-situ doping the first source/drain regions during an epitaxial growth process.
13. 13 . The method of claim 12 , wherein forming the second source/drain regions comprises performing an implantation process.
14. 14 . The method of claim 10 , wherein forming the first source/drain regions comprises performing an implantation process.
15. 15 . The method of claim 10 , wherein doping the second channel region comprises implanting the second channel region simultaneously with implanting the first channel region.
16. 16 . A method of manufacturing a semiconductor device, comprising: doping an entirety of a first channel region of a first transistor with a first dopant having a first conductivity type; doping an entirety of a second channel region of a second transistor with a second dopant having the first conductivity type; growing first source/drain regions of the first transistor, wherein the channel region of the first transistor is an entire area between the first source/drain regions configured to permit current flow in response to a gate of the first transistor receiving a threshold voltage, wherein a depth of the first channel region is equal to or greater than a depth of the first source/drain regions; doping first source/drain regions to have the first conductivity type; forming second source/drain regions of the second transistor to have a second conductivity type, wherein the second conductivity is different from the first conductivity type; forming a well having the second conductivity type, wherein the first channel region is between a bottommost surface of the first source/drain regions and the well; depositing a first work function layer over the first channel region; and depositing a second work function layer over the second channel region, wherein the first work function layer and the second work function layer comprise a same material.
17. 17 . The method of claim 16 , wherein doping the second channel region comprises implanting the second channel region simultaneously with implanting the first channel region.
18. 18 . The method of claim 16 , wherein doping the first source/drain regions comprises doping the first source/drain regions simultaneously with growing the first source/drain regions.
19. 19 . The method of claim 16 , wherein doping the first channel region comprises doping the first channel region of a nanowire field effect transistor (NWFET).
20. 20 . The method of claim 16 , wherein doping the first channel region comprises doping the first channel region with the first dopant being a same material as the second dopant.

Description

PRIORITY CLAIM The instant application is a divisional of U.S. application Ser. No. 15/583,126, filed May 1, 2017, now U.S. Pat. No. 10,553,494, issued Feb. 4, 2020, which claims priority to a non-provisional application claiming priority to Provisional Application No. 62/427,548, filed Nov. 29, 2016, the entire contents of which are incorporated by reference herein. BACKGROUND Semiconductor devices having smaller channel lengths experience heightened levels of device failures associated with hot carrier injection (HCI), time-dependent dielectric breakdown (TDDB), and bias threshold instability (BTI) in comparison with semiconductor devices having longer channel lengths. As technology nodes for semiconductor devices decrease, thinner gate dielectric layers are used to reduce short channel effects. Gate-induced dielectric loss (GIDL) is more prevalent with semiconductor devices having thin gate dielectric layers adjoining field effect transistors (FETs) than with other semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 is a cross-sectional view of an N-type accumulation mode field effect transistor (FET), according to some embodiments. FIG. 2 is a cross-sectional view of a P-type accumulation mode FET, according to some embodiments. FIG. 3A is a perspective view of a fin field effect transistor (FinFET), according to some embodiments. FIGS. 3B-3C are cross-sectional views of a FinFET along corresponding cross-sectional lines A-A and B-B as shown in FIG. 3A, according to some embodiments. FIG. 4A is a perspective view of a nanowire field effect transistor (NWFET), according to some embodiments. FIGS. 4B-4C are cross-sectional views of a NWFET along corresponding cross-sectional lines C-C and D-D as shown in FIG. 4A, according to some embodiments. FIG. 5 is a flowchart of a method of forming a FET, according to some embodiments. FIGS. 6A-6D are cross-sectional views of a FinFET during various stages of a manufacturing process, according to some embodiments. FIGS. 7A-7F are cross-sectional views of a NWFET during various stages of a manufacturing process, according to some embodiments. FIG. 8 is a perspective view of multiple NWFETs according to some embodiments. DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Aging-related breakdown of semiconductor devices includes breakdown mechanisms such as hot carrier injection (HCI), time-dependent dielectric breakdown (TDDB), and bias temperature instability. Rates of aging-related FET breakdown increase in conjunction with cumulative exposure of transistors to elevated temperatures and cumulative flow of electrical current. Aging-related transistor breakdown by HCI, TDDB, and BTI is enhanced with increased current density at the interface of a channel and a gate dielectric material in a transistor. One factor in decreasing rates of aging-related FET breakdown is reducing electrical fields in the region of the gate dielectric material in the FETs. Another factor in decreasing rates of aging-related FET breakdown is conducting less current at the interface of the gate di