US-12622045-B2 - Semiconductor power devices having doped and silicided polysilicon temperature sensors therein

Abstract

A power device includes a semiconductor substrate having first and second current carrying terminals on respective first and second opposing surfaces thereof. A silicided polysilicon temperature sensor and silicided polysilicon gate electrode are provided on the first surface. A source region of first conductivity type and a shielding region of second conductivity type are provided in the semiconductor substrate. The shielding region forms a P-N rectifying junction with the source region, and extends between the silicided polysilicon temperature sensor and the second current carrying terminal. A field oxide insulating region is provided, which extends between the shielding region and the silicided polysilicon temperature sensor.

Inventors

• Bantval Jayant Baliga

Assignees

• NORTH CAROLINA STATE UNIVERSITY

Dates

Publication Date

20260505

Application Date

20220802

Claims (20)

1. 1 . A power semiconductor device, comprising: a semiconductor substrate having a first current carrying terminal on a first surface thereof and a second current carrying terminal on a second surface thereof opposing the first surface; and a silicided polysilicon temperature sensor on the first surface.
2. 2 . The device of claim 1 , wherein a first terminal of the silicided polysilicon temperature sensor is electrically connected to the first current carrying terminal.
3. 3 . The device of claim 1 , further comprising a silicided polysilicon gate electrode on the first surface.
4. 4 . The device of claim 1 , further comprising: a source region of first conductivity type in the semiconductor substrate, which is electrically connected to a first terminal of the silicided polysilicon temperature sensor; and a shielding region of second conductivity type in the semiconductor substrate, which extends between the silicided polysilicon temperature sensor and the second current carrying terminal.
5. 5 . The device of claim 1 , wherein a resistance of the silicided polysilicon temperature sensor monotonically increases with temperature.
6. 6 . The device of claim 5 , wherein the resistance of the silicided polysilicon temperature sensor is in a range from 1Ω/square to 5Ω/square at 25° C.
7. 7 . The device of claim 5 , wherein the silicided polysilicon temperature sensor is doped with a dopant of first conductivity type; and wherein the resistance of the silicided polysilicon temperature sensor increases at a rate within a range from 0.075%/° C. to 0.175%/° C. in an operating temperature range.
8. 8 . The device of claim 1 , wherein the first and second current carrying terminals are source and drain terminals of an insulated-gate field effect transistor (IGFET), respectively.
9. 9 . The device of claim 1 , wherein the first and second current carrying terminals are respective terminals of an insulated-gate transistor.
10. 10 . The device of claim 9 , wherein a first terminal of the silicided polysilicon temperature sensor is electrically connected to the first current carrying terminal of the insulated-gate transistor.
11. 11 . The device of claim 1 , further comprising a third current carrying terminal on the first surface of the semiconductor substrate; and a second silicided polysilicon temperature sensor on the first surface; and wherein the power semiconductor device is a silicon carbide (SiC) bi-directional field effect transistor (BiDFET).
12. 12 . The device of claim 11 , wherein first and second terminals of the second silicided polysilicon temperature sensor are independent of the first, second and third current carrying terminals.
13. 13 . The device of claim 1 , wherein the silicided polysilicon temperature sensor comprises a polysilicon layer and a silicide layer on the polysilicon layer.
14. 14 . A power semiconductor device, comprising: a silicon carbide (SiC) substrate having a first source electrode of a first field effect transistor (FET) and a second source electrode of a second FET at spaced-apart locations on a first surface thereof; and first and second silicided polysilicon temperature sensors associated with the first and second FETS, respectively, on the first surface.
15. 15 . The device of claim 14 , wherein first and second terminals of each of the first and second silicided polysilicon temperature sensors are independent of the first and second source electrodes.
16. 16 . The device of claim 14 , wherein a first terminal of the first silicided polysilicon temperature sensor is electrically connected to the first source electrode; and wherein a first terminal of the second silicided polysilicon temperature sensor is electrically connected to the second source electrode.
17. 17 . The device of claim 16 , wherein a first gate electrode of the first FET comprises silicided polysilicon derived from a silicided polysilicon layer; and wherein the first and second silicided polysilicon temperature sensors are derived from the same silicided polysilicon layer.
18. 18 . The device of claim 14 , wherein a first gate electrode of the first FET comprises silicided polysilicon derived from a silicided polysilicon layer; and wherein the first and second silicided polysilicon temperature sensors are derived from the same silicided polysilicon layer.
19. 19 . A power semiconductor device, comprising: a semiconductor substrate having an insulated-gate transistor therein; and a silicided polysilicon temperature sensor having a first current carrying terminal electrically connected to a first current carrying terminal of the insulated-gate transistor.
20. 20 . The device of claim 19 , wherein a gate electrode of the insulated-gate transistor comprises silicided polysilicon derived from a silicided polysilicon layer; and wherein the silicided polysilicon temperature sensor is derived from the same silicided polysilicon layer.

Description

REFERENCE TO PRIORITY APPLICATIONS This application claims priority to U.S. Provisional Application Ser. No. 63/245,521, filed Sep. 17, 2021, and is a continuation-in-part (CIP) of U.S. application Ser. No. 17/418,309, filed Jun. 25, 2021, the disclosures of which are hereby incorporated herein by reference. STATEMENT OF GOVERNMENT INTEREST The present invention was made with United States Government support under Grant No. DE-EE0008345 awarded by the United States Department of Energy's Office of Energy Efficiency and Renewable Energy (DOE/EERE). The United States Government has certain rights in the invention. FIELD OF THE INVENTION The present invention relates to semiconductor devices and, more particularly, to power devices having semiconductor-based switches therein that support high currents and high temperature in high power applications. BACKGROUND OF THE INVENTION Conventional semiconductor switching devices that are frequently utilized in high power switching applications to control high current loads may include wide bandgap power transistors, such as silicon carbide (SiC) power MOSFETs. As shown by FIGS. 1A-1B, a planar-gate inversion-mode SiC power MOSFET 10a having a P-type gate-controlled active region (P-BASE) and a planar-gate accumulation-mode SiC power MOSFET 10b having an N-type gate-controlled active region (N-BASE) utilize relatively highly doped P+ shielding regions within an N-type substrate containing a vertical N-type voltage-supporting drift region therein. Related power MOSFETs that utilize P+ shielding regions are disclosed in U.S. Pat. Nos. 6,791,143; 7,041,559 to B. Jayant Baliga, the disclosures of which are hereby incorporated herein by reference. As shown by FIG. 1C, SiC power MOSFETs 10c may also utilize trench-based gate electrodes having vertical sidewalls, which extend adjacent P-type base regions (P-BASE), and bottoms, which extend adjacent P+ shielding regions. Similarly, FIG. 1D illustrates a silicon (Si) trench-gate insulated-gate bipolar transistor (IGBT) for high power applications, which contains a P-type collector region adjacent a bottom surface of a semiconductor substrate. Related power MOSFETs and IGBTs having trench-based gate electrodes are disclosed in U.S. Pat. Nos. 5,912,497, 6,649,975 and 6,764,889 to B. Jayant Baliga, the disclosures of which are hereby incorporated herein by reference. In addition, U.S. Pat. No. 5,396,085 to B. Jayant Baliga, entitled “Silicon Carbide Switching Device with Rectifying-Gate,” discloses, among other things, hybrid switching devices having silicon MOSFETs and silicon carbide JFETs (or MESFETs) integrated together as three-terminal hybrid devices. Silicon Power MOSFET and IGBT: Many silicon power MOSFETs and IGBTs are manufactured as n-channel devices due to their generally superior electrical performance when compared with p-channel devices. Typically, these n-channel MOS-gated devices are made using heavily n-type doped polysilicon gate electrodes because of better performance compared with p-type polysilicon gate electrodes, as demonstrated in a textbook by B. Jayant Baliga, entitled, “Fundamentals of Power Semiconductor Devices”, Second Edition, Springer-Science 2019. In particular, Chapter 6 of this textbook demonstrates that the doping concentration of the P-base region of n-channel devices can be larger when using N+ polysilicon compared with P+ polysilicon to achieve the same desired value for the threshold voltage. (See, e.g., FIG. 6.28). Moreover, the larger P-base doping advantageously suppresses reach-through of the electric field, thereby allowing shorter channel lengths, which reduce the on-state resistance. Silicon Carbide Power MOSFETs: Silicon carbide power MOSFET products are typically manufactured using n-channel devices due to their much superior performance compared with otherwise equivalent p-channel devices. These SiC n-channel products are typically made using heavily n-type doped polysilicon gate electrodes because of their better performance compared with p-type polysilicon gate electrodes, as demonstrated in a textbook by B. Jayant Baliga, entitled “Gallium Nitride and Silicon Carbide Power Devices”, World Scientific Publishers 2017. In particular, as demonstrated in Chapter 11 of this textbook, the doping concentration of the P-base region of n-channel devices is larger when using N+ polysilicon compared with P+ polysilicon to achieve the same desired value for threshold voltage. (See, e.g., FIG. 11.10). Advantageously, this larger doping of the P-base suppresses reach-through of the electric field, which allows for shorter channel length and thereby reduces the on-state resistance. Silicided Gate Electrode Material for Power Devices: When manufacturing Si and SiC power devices, the polysilicon gate electrode layer is typically deposited using low pressure chemical vapor deposition (LPCVD). As will be understood by those skilled in the art, an n-type dopant, typically phosphorus (P), is added