US-12622046-B2 - Semiconductor device, inverter circuit, drive device, vehicle, and elevator

US12622046B2US 12622046 B2US12622046 B2US 12622046B2US-12622046-B2

Abstract

A semiconductor device of an embodiment includes a SiC layer including a first face parallel to first direction and second direction perpendicular to the first direction, a trench extending in the first direction, a gate electrode, an n-type first SiC region, a p-type second SiC region between the first SiC region and the trench, extending in the second direction, an n-type third SiC region extending in the second direction, and alternately and repeatedly provided with the second SiC region in the first direction, a p-type fourth SiC region between the third SiC region and the first face, an n-type fifth SiC region between the fourth SiC region and the first face. The first face is inclined with respect to a (0001) face by 0.1 to 8 degrees in a <11-20> direction, and the first direction is along the <11-20> direction, and the second direction is along a <1-100> direction.

Inventors

Tatsuo Shimizu

Assignees

KABUSHIKI KAISHA TOSHIBA

Dates

Publication Date: 20260505
Application Date: 20230302
Priority Date: 20220916

Claims (14)

1 . A semiconductor device comprising: a silicon carbide layer including a first face parallel to a first direction and a second direction perpendicular to the first direction and a second face parallel to the first face; a trench provided in the silicon carbide layer, extending in the first direction on the first face, the trench repeatedly provided in the second direction at a first period; a gate electrode provided in the trench; a gate insulating layer provided between the gate electrode and the silicon carbide layer; an n-type first silicon carbide region provided in the silicon carbide layer; a p-type second silicon carbide region provided in the silicon carbide layer, the p-type second silicon carbide region provided between the n-type first silicon carbide region and the trench, the p-type second silicon carbide region extending in the second direction in a face parallel to the first face, the p-type second silicon carbide region repeatedly provided in the first direction at a second period; an n-type third silicon carbide region provided in the silicon carbide layer, the n-type third silicon carbide region provided between the n-type first silicon carbide region and the trench, the n-type third silicon carbide region extending in the second direction in the face parallel to the first face, the n-type third silicon carbide region alternately and repeatedly provided with the p-type second silicon carbide region in the first direction at the second period; a p-type fourth silicon carbide region provided in the silicon carbide layer, the p-type fourth silicon carbide region provided between the p-type second silicon carbide region and the first face, the p-type fourth silicon carbide region provided between the n-type third silicon carbide region and the first face, the p-type fourth silicon carbide region provided between one of the trench and another of the trench immediately neighboring the one of the trench; an n-type fifth silicon carbide region provided in the silicon carbide layer, the n-type fifth silicon carbide provided between the p-type fourth silicon carbide region and the first face; a p-type sixth silicon carbide region provided in the silicon carbide layer, the p-type sixth silicon carbide region provided between the n-type third silicon carbide region and the trench, the p-type sixth silicon carbide region being in contact with a bottom surface of the trench, the p-type sixth silicon carbide region extending in the first direction; a first electrode provided on a side of the first face with respect to the silicon carbide layer, the first electrode electrically connected to the p-type fourth silicon carbide region and the n-type fifth silicon carbide region; and a second electrode provided on a side of the second face with respect to the silicon carbide layer, wherein the first face is inclined with respect to a (0001) face at an angle equal to or more than 0.1 degrees and equal to or less than 8 degrees in a <11-20> direction, and the first direction is along the <11-20> direction, and the second direction is along a <1-100> direction.
2 . The semiconductor device according to claim 1 , wherein the second period is more than the first period.
3 . The semiconductor device according to claim 1 , further comprising: an n-type eighth silicon carbide region provided in the silicon carbide layer, the n-type eighth silicon carbide region provided between the p-type second silicon carbide region and the p-type fourth silicon carbide region.
4 . The semiconductor device according to claim 1 , further comprising: an n-type ninth silicon carbide region provided in the silicon carbide layer, the n-type ninth silicon carbide region provided between the n-type first silicon carbide region and the p-type second silicon carbide region, the n-type ninth silicon carbide region being in contact with the p-type second silicon carbide region, an n-type impurity concentration of the n-type ninth silicon carbide region being more than an n-type impurity concentration of the n-type third silicon carbide region, the n-type impurity concentration of the n-type ninth silicon carbide region being less than an n-type impurity concentration of the n-type first silicon carbide region.
5 . The semiconductor device according to claim 1 , wherein a length of the p-type second silicon carbide region in a third direction from the first face to the second face is more than a width of the p-type second silicon carbide region in the first direction.
6 . The semiconductor device according to claim 1 , wherein a width of the n-type third silicon carbide region in the first direction is more than a width of the p-type second silicon carbide region in the first direction.
7 . An inverter circuit comprising the semiconductor device according to claim 1 .
8 . A drive device comprising the semiconductor device according to claim 1 .
9 . A vehicle comprising the semiconductor device according to claim 1 .
10 . An elevator comprising the semiconductor device according to claim 1 .
11 . A semiconductor device comprising: a silicon carbide layer including a first face parallel to a first direction and a second direction perpendicular to the first direction and a second face parallel to the first face; a trench provided in the silicon carbide layer, extending in the first direction on the first face, the trench repeatedly provided in the second direction at a first period; a gate electrode provided in the trench; a gate insulating layer provided between the gate electrode and the silicon carbide layer; an n-type first silicon carbide region provided in the silicon carbide layer; a p-type second silicon carbide region provided in the silicon carbide layer, the p-type second silicon carbide region provided between the n-type first silicon carbide region and the trench, the p-type second silicon carbide region extending in the second direction in a face parallel to the first face, the p-type second silicon carbide region repeatedly provided in the first direction at a second period; an n-type third silicon carbide region provided in the silicon carbide layer, the n-type third silicon carbide region provided between the n-type first silicon carbide region and the trench, the n-type third silicon carbide region extending in the second direction in the face parallel to the first face, the n-type third silicon carbide region alternately and repeatedly provided with the p-type second silicon carbide region in the first direction at the second period; a p-type fourth silicon carbide region provided in the silicon carbide layer, the p-type fourth silicon carbide region provided between the p-type second silicon carbide region and the first face, the p-type fourth silicon carbide region provided between the n-type third silicon carbide region and the first face, the p-type fourth silicon carbide region provided between one of the trench and another of the trench immediately neighboring the one of the trench; an n-type fifth silicon carbide region provided in the silicon carbide layer, the n-type fifth silicon carbide provided between the p-type fourth silicon carbide region and the first face; a p-type seventh silicon carbide region provided in the silicon carbide layer, the p-type seventh silicon carbide region provided between the fourth silicon carbide region and the trench, and between the n-type fifth silicon carbide region and the trench, and repeatedly disposed in the first direction at a third period; a first electrode provided on a side of the first face with respect to the silicon carbide layer, the first electrode electrically connected to the p-type fourth silicon carbide region and the n-type fifth silicon carbide region; and a second electrode provided on a side of the second face with respect to the silicon carbide layer, wherein the first face is inclined with respect to a (0001) face at an angle equal to or more than 0.1 degrees and equal to or less than 8 degrees in a <11-20> direction, and the first direction is along the <11-20> direction, and the second direction is along a <1-100> direction.
12 . The semiconductor device according to claim 11 , wherein the p-type seventh silicon carbide region is in contact with the p-type second silicon carbide region.
13 . The semiconductor device according to claim 11 , wherein the second period is more than the first period, and the third period is more than the second period.
14 . A semiconductor device comprising: a silicon carbide layer including a first face parallel to a first direction and a second direction perpendicular to the first direction and a second face parallel to the first face; a trench provided in the silicon carbide layer, extending in the first direction on the first face, the trench repeatedly provided in the second direction at a first period; a gate electrode provided in the trench; a gate insulating layer provided between the gate electrode and the silicon carbide layer; an n-type first silicon carbide region provided in the silicon carbide layer; a p-type second silicon carbide region provided in the silicon carbide layer, the p-type second silicon carbide region provided between the n-type first silicon carbide region and the trench, the p-type second silicon carbide region extending in the second direction in a face parallel to the first face, the p-type second silicon carbide region repeatedly provided in the first direction at a second period; an n-type third silicon carbide region provided in the silicon carbide layer, the n-type third silicon carbide region provided between the n-type first silicon carbide region and the trench, the n-type third silicon carbide region extending in the second direction in the face parallel to the first face, the n-type third silicon carbide region alternately and repeatedly provided with the p-type second silicon carbide region in the first direction at the second period; a p-type fourth silicon carbide region provided in the silicon carbide layer, the p-type fourth silicon carbide region provided between the p-type second silicon carbide region and the first face, the p-type fourth silicon carbide region provided between the n-type third silicon carbide region and the first face, the p-type fourth silicon carbide region provided between one of the trench and another of the trench immediately neighboring the one of the trench; an n-type fifth silicon carbide region provided in the silicon carbide layer, the n-type fifth silicon carbide provided between the p-type fourth silicon carbide region and the first face; a first electrode provided on a side of the first face with respect to the silicon carbide layer, the first electrode electrically connected to the p-type fourth silicon carbide region and the n-type fifth silicon carbide region; and a second electrode provided on a side of the second face with respect to the silicon carbide layer, wherein the first face is inclined with respect to a (0001) face at an angle equal to or more than 0.1 degrees and equal to or less than 8 degrees in a <11-20> direction, and the first direction is along the <11-20> direction, the second direction is along a <1-100> direction, and the p-type second silicon carbide region includes a first region and a second region, the second region is provided between the first region and the p-type fourth silicon carbide region, and a p-type impurity concentration of the second region is more than a p-type impurity concentration of the first region.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2022-148329, filed on Sep. 16, 2022, the entire contents of which are incorporated herein by reference. FIELD Embodiments described herein relate generally to a semiconductor device, an inverter circuit, a drive device, a vehicle, and an elevator. BACKGROUND Silicon carbide (SiC) is expected as a material for a next-generation semiconductor device. The silicon carbide has excellent physical properties such as a band gap of about 3 times, a breakdown field strength of about times, and a thermal conductivity of about 3 times those of silicon. These physical properties are utilized, and thus, a semiconductor device capable of being operated at a high temperature with low loss can be realized. A metal oxide semiconductor field effect transistor (MOSFET) using silicon carbide is required to reduce an on-resistance. In order to reduce the on-resistance of the MOSFET, a vertical MOSFET having a trench-gate structure in which a gate electrode is provided in a trench is adopted. In the vertical MOSFET, there is a super junction structure (hereinafter, also referred to as a “SJ structure”) in which a p-type region and an n-type region are alternately arranged in a lateral direction as a structure for achieving both a high breakdown voltage and a low on-resistance. The SJ structure relaxes electric field intensity in a semiconductor by a depletion layer extending in the lateral direction in the p-type region and the n-type region, and realizes the high breakdown voltage of the MOSFET. At the same time, the low on-resistance of the MOSFET can be realized by increasing a concentration of an n-type impurity region. The vertical MOSFET having a trench-gate structure and the SJ structure are combined to further scale-down the SJ structure, and thus, the on-resistance can be further reduced. A vertical MOSFET using silicon carbide includes a pn junction diode as a built-in diode. For example, the MOSFET is used as a switching element connected to an inductive load. In this case, even though the MOSFET is turned off, a reflux current can flow by using the built-in diode. However, when the reflux current flows using the built-in diode, there is a problem that a stacking fault grows in a silicon carbide layer due to recombination energy of carriers and an on-resistance of the MOSFET increases. An increase in the on-resistance of the MOSFET causes a decrease in reliability of the MOSFET. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view of a semiconductor device of a first embodiment; FIG. 2 is a schematic cross-sectional view of the semiconductor device of the first embodiment; FIG. 3 is a schematic cross-sectional view of the semiconductor device of the first embodiment; FIG. 4 is a schematic cross-sectional view of the semiconductor device of the first embodiment; FIG. 5 is a schematic plan view of the semiconductor device of the first embodiment; FIG. 6 is a schematic cross-sectional view of the semiconductor device of the first embodiment; FIG. 7 is a diagram illustrating a crystal structure of a silicon carbide semiconductor; FIG. 8 is a schematic cross-sectional view of a semiconductor device of a comparative example; FIG. 9 is a schematic cross-sectional view of a semiconductor device of a comparative example; FIG. 10 is a schematic cross-sectional view of the semiconductor device of the comparative example; FIG. 11 is a schematic cross-sectional view of the semiconductor device of the comparative example; FIG. 12 is a schematic cross-sectional view of the semiconductor device of the comparative example; FIG. 13 is a schematic cross-sectional view of the semiconductor device of the comparative example; FIG. 14 is an equivalent circuit diagram of the semiconductor devices of the comparative example and the first comparative example; FIG. 15 is an explanatory diagram of functions and effects of the semiconductor device of the first embodiment; FIG. 16 is an explanatory diagram of the functions and effects of the semiconductor device of the first embodiment; FIG. 17 is an explanatory diagram of the functions and effects of the semiconductor device of the first embodiment; FIG. 18 is an explanatory diagram of the functions and effects of the semiconductor device of the first embodiment; FIG. 19 is a schematic cross-sectional view of a semiconductor device of a first modification example of the first embodiment; FIG. 20 is a schematic cross-sectional view of the semiconductor device of the first modification example of the first embodiment; FIG. 21 is a schematic cross-sectional view of a semiconductor device of a second modification example of the first embodiment; FIG. 22 is a schematic cross-sectional view of the semiconductor device of a second modification example of the first embodiment; FIG. 23 is a schematic diagram of a drive device of a second embod