US-12622047-B2 - Schottky diode integrated into superjunction power MOSFETs

Abstract

A trench metal-oxide-semiconductor field-effect transistor (MOSFET) device comprises an active cell area including a plurality of superjunction trench power MOSFETs formed in an epitaxial layer. Each MOSFET includes source and body regions and a contact trench formed between first and second gate trenches. A region of the epitaxial layer between the gate trenches extends to the top surface of the epitaxial layer. An insulated gate electrode is formed in each gate trench. At least a portion of the contact trench extends from a top surface of the epitaxial layer to a depth that is shallower than the bottom of the body region.

Inventors

• Yi Su
• Madhur Bobde

Assignees

• ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.

Dates

Publication Date

20260505

Application Date

20221101

Claims (20)

1. 1 . A trench metal-oxide-semiconductor field-effect transistor (MOSFET) device, comprising: an active cell area having one or more devices each of the one or more devices including a plurality of alternating N columns and P columns extending in an epitaxial layer above a heavily doped substrate layer forming a superjunction structure; first and second gate trenches extending from a top surface of the epitaxial layer into the N columns of the superjunction structure; an insulated gate electrode formed in each of the first and second gate trenches; a source region and a body region formed between the first and second gate trenches, wherein a bottom of the body region reaches a top of a P column in the plurality of alternating N columns and P columns; a region of the epitaxial layer extending to the top surface of the epitaxial layer between a portion of the first and second gate trenches; a contact trench between the first gate trench and the second gate trench, wherein the contact trench is aligned to a corresponding P column in the plurality of alternating N columns and P columns, wherein at least a portion of the contact trench extends from a top surface of the epitaxial layer to a depth that is shallower than the bottom of the body region; and a Schottky diode area having one or more Schottky diodes each of the one or more devices including a plurality of alternating N columns and P columns extending in the epitaxial layer above the heavily doped substrate layer forming a superjunction structure, first and second Schottky gate trenches extending from a top surface of the epitaxial layer into the N columns of the superjunction structure, an insulated gate electrode formed in each of the first and second Schottky gate trenches; a region of the epitaxial layer extending to the top surface of the epitaxial layer between a portion of the first and second gate trenches, a Schottky contact trench between the first gate trench and the second gate trench, wherein the Schottky contact trench is aligned to a corresponding P column in the plurality of alternating N columns and P columns, and a contact implant formed beneath a bottom of the Schottky contact trench.
2. 2 . The device of claim 1 , further comprising a contact implant formed beneath a bottom of the portion of the contact trench.
3. 3 . The device of claim 2 , further comprising an electrode inside the second contact trench that forms electrical contact to a corresponding P column of the plurality of alternating N columns and P columns.
4. 4 . The device of claim 2 , wherein the portion of the contact trench beneath which the contact implant is formed is wider than another portion of the contact trench.
5. 5 . The device of claim 2 , wherein the contact trench has a width of about 0.5 to 0.7 microns.
6. 6 . The device of claim 2 , wherein a gap between the portion of the contact trench beneath which the contact implant is formed and an adjacent gate trench of the first and second gate trenches is less than 0.2 microns.
7. 7 . The device of claim 1 , wherein an operating voltage of the device is between 8 V to 40 V and each of the plurality of the gate trenches has a pitch between 1.3 and 1.7 microns.
8. 8 . The device of claim 1 , wherein an operating voltage of the device is 30 V and each of the plurality of the gate trenches has a pitch between 1.3 and 1.7 microns.
9. 9 . The device of claim 1 , wherein an operating voltage of the device is over 100 V and each of the plurality of the gate trenches has a pitch between 3.5 and 5 microns.
10. 10 . The device of claim 1 , further comprising a shield electrode in a lower portion under the insulated gate electrode in an upper portion in each of the plurality of the first and second gate trenches.
11. 11 . The device of claim 1 , wherein no source or body region is formed between the first and second Schottky gate trenches.
12. 12 . A method of fabricating a trench metal-oxide-semiconductor field-effect transistor (MOSFET) device, the method comprising: forming a plurality of alternating N columns and P columns extending in an epitaxial layer above a heavily doped substrate layer forming a superjunction structure; forming first and second gate trenches from a top surface of the epitaxial layer that extend into the N columns of the superjunction structure; forming an insulated gate electrode in each of the first and second gate trenches; forming a source region and a body region between the first and second gate trenches, wherein a bottom of the body region reaches a top of a P column in the plurality of alternating N columns and P columns, wherein a region of the epitaxial layer extends to the top surface of the epitaxial layer between a portion of the first and second gate trenches; forming a contact trench between the first gate trench and the second gate trench, wherein the contact trench is aligned to corresponding P columns in the plurality of alternating N columns and P columns, wherein a portion of the contact trench extends from a top surface of the epitaxial layer to a depth that is shallower than the bottom of the body region; and forming a Schottky diode area having one or more Schottky diodes each of the one or more Schottky diodes including a plurality of alternating N columns and P columns extending in the epitaxial layer above the heavily doped substrate layer forming a superjunction structure, first and second Schottky gate trenches extending from a top surface of the epitaxial layer into the N columns of the superjunction structure, an insulated gate electrode formed in each of the first and second Schottky gate trenches; a region of the epitaxial layer extending to the top surface of the epitaxial layer between a portion of the first and second Schottky gate trenches, a Schottky contact trench between the first Schottky gate trench and the second Schottky gate trench, wherein the Schottky contact trench is aligned to a corresponding P column in the plurality of alternating N columns and P columns, and a contact implant formed beneath a bottom of the Schottky contact trench.
13. 13 . The method of claim 12 , wherein the portion of the contact trench is wider than another portion of the contact trench.
14. 14 . The method of claim 13 , wherein a gap between the portion of the contact trench and an adjacent gate trench of the first and second gate trenches is less than 0.2 microns.
15. 15 . The method of claim 12 , wherein forming the first and second gate trenches includes applying a gate trench mask on the drift region which uncovers locations for gate trench openings for the first and second gate trenches.
16. 16 . The method of claim 12 , wherein forming the first and second gate trenches includes applying a gate trench mask on the epitaxial layer which uncovers locations for gate trench openings for portions of the first and second gate trenches and covers locations for other portions of the first and second gate trenches.
17. 17 . The method of claim 12 , wherein forming the body region includes applying a body mask that covers locations corresponding to portions of the first and second gate trenches and leaves locations corresponding to other portions of the first and second gate trenches uncovered.
18. 18 . The method of claim 12 , further comprising forming a contact implant region underneath the portion of the contact trench by performing an angle implant through an opening of the portion of the contact trench.
19. 19 . The method of claim 18 , wherein forming the contact implant region includes performing a Shannon implant through the opening of the portion of the contact trench.
20. 20 . The method of claim 12 , further comprising forming an insulated gate electrode in an upper portion of each of the first and second gate trenches and forming an insulated shield electrode in a lower portion of each of the first and second gate trenches.

Description

CLAIM OF PRIORITY This application is a continuation of U.S. patent application Ser. No. 17/039,703 filed Sep. 30, 2020, the entire contents of which are incorporated herein by reference. U.S. patent application Ser. No. 17/039,703 is a continuation of U.S. patent application Ser. No. 15/843,327 filed Dec. 15, 2017, the entire contents of which are incorporated herein by reference. FIELD OF THE DISCLOSURE This disclosure relates in general to metal-oxide-semiconductor field-effect transistors (MOSFETs) and more specifically to a superjunction power MOSFET and a method for fabricating the same. BACKGROUND OF INVENTION Integrated circuits, such as microprocessors and memory devices, include many metal-oxide-semiconductor field-effect transistors (MOSFETs). MOSFETs are typically used for amplifying or switching electronic signals. A MOSFET device for power switching is sometimes referred to as a power MOSFET. Most power MOSFETs feature a vertical structure with source and drain regions on opposite sides of a gate trench filled with polysilicon as gate electrodes. Power MOSFET devices typically contain multiple individual MOSFET structures arranged in active cells. Schottky diodes are commonly used in low voltage power MOSFET devices (e.g., less than 40 volts). They help improve the diode recovery portion of the device switching behavior and reduce power loss due to their relatively lower forward voltage. In addition, the fast turn on and turn off of MOSFETs in some applications, such as DC-DC converter, may cause switch-node ringing with voltage spikes. A Schottky diode clamped to the MOSFET device may reduce these voltage spikes. On the other hand, superjunction structures have been employed for high voltage power MOSFET devices (e.g., over 500 volts) to provide a way to achieve low on-resistance (Rds-on), while maintaining a high off-state breakdown voltage (BV). In a power MOSFET, it is desirable to reduce the resistance of the device during conduction (Rds-on) and improve its breakdown voltage (BV). However, the on-resistance (Rds-on) and the breakdown voltage (BV) are in a tradeoff relation with respect to each other. That is, the on-resistance increases dramatically with an increase in breakdown voltage (Rds-on) (BV) for a conventional transistor. Since superjunction devices include alternating p-type and n-type doped columns arranged in parallel and connected to each other in the drift region, these charge balanced columns deplete one another laterally when a reverse-bias voltage is applied to between the drain and the source. As such, superjunction devices can withstand a high breakdown voltage in the vertical direction while having significantly lower on-resistance (Rds-on) than a conventional MOSFET device for the (Rds-on) same high breakdown voltage (BV) (or conversely may have a significantly higher breakdown voltage BV than a conventional MOSFET for a given on-resistance Rds-on). It is within this context that embodiments of the present invention arise. BRIEF DESCRIPTION OF THE DRAWINGS Objects and advantages of aspects of the present disclosure will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which: FIG. 1 is an overhead view of portions of a power MOSFET device according to aspects of the present disclosure. FIG. 2 is a cross-sectional view of portions of a power MOSFET device according to aspects of the present disclosure. FIG. 3 is a cross-sectional view of portions of a power MOSFET device according to aspects of the present disclosure. FIG. 4 is a cross-sectional view of portions of a power MOSFET device according to aspects of the present disclosure. FIG. 5 is a cross-sectional view of portions of a power MOSFET device according to aspects of the present disclosure. FIG. 6 is a flow chart illustrating a fabrication of a power MOSFET device according to aspects of the present disclosure. DESCRIPTION OF THE SPECIFIC EMBODIMENTS In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. For convenience, use of + or − after a designation of conductivity or net impurity carrier type (p or n) refers generally to a relative degree of concentration of designated type of net impurity carriers within a semiconductor material. In general terms, an n+ material has a higher n type net dopant (e.g., electron) concentration than an n material, and an n material has a higher carrier concentration than an n− material. Similarly, a p+ material has a higher p type net dopant (e.g., hole) concentration than a p material, and a p material has a higher concentration than a p− material. It is noted that what is relevant is the net concentration of the carriers, not necessarily dopants. For example, a material may be heavily doped with n-type dopants but still have a relatively low net