US-12622049-B2 - Semiconductor device

US12622049B2US 12622049 B2US12622049 B2US 12622049B2US-12622049-B2

Abstract

A semiconductor device is provided. The semiconductor device includes an active pattern extending in a first horizontal direction, a plurality of lower nanosheets stacked on the active pattern and spaced apart from one another in a vertical direction, a separation layer on the plurality of lower nanosheets, a plurality of upper nanosheets stacked on the separation layer and spaced apart from one another in the vertical direction, a gate electrode extending on the active pattern in a second horizontal direction, the gate electrode surrounding each of the plurality of lower nanosheets, the separation layer and the plurality of upper nano sheets, and a first conductive layer between the gate electrode and each of a top surface and a bottom surface of the plurality of upper nanosheets. The first conductive layer is not between the gate electrode and sidewalls of the plurality of upper nanosheets.

Inventors

Kyu Man HWANG
Sung Il Park
Jin Chan YUN
Dong Kyu Lee

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260505
Application Date: 20230411
Priority Date: 20220916

Claims (20)

1 . A semiconductor device comprising: an active pattern extending in a first horizontal direction on a substrate; a plurality of lower nanosheets stacked on the active pattern to be spaced apart from one another in a vertical direction; a separation layer on the plurality of lower nanosheets; a plurality of upper nanosheets stacked on the separation layer to be spaced apart from one another in the vertical direction; a gate electrode on the active pattern and extending in a second horizontal direction, which is different from the first horizontal direction, the gate electrode surrounding each of the plurality of lower nanosheets, the separation layer, and the plurality of upper nanosheets; and a first conductive layer between the gate electrode and each of a top surface of and a bottom surface of the plurality of upper nanosheets, the first conductive layer is not between the gate electrode and sidewalls in the second horizontal direction of the plurality of upper nanosheets.
2 . The semiconductor device of claim 1 , wherein the first conductive layer is not between the gate electrode and the plurality of lower nanosheets.
3 . The semiconductor device of claim 1 , further comprising: a dummy nanosheet spaced apart from the plurality of upper nanosheets in the vertical direction and surrounded by the gate electrode, the dummy nanosheet including an insulating material.
4 . The semiconductor device of claim 3 , wherein the first conductive layer is between the gate electrode and a bottom surface of the dummy nanosheet, the first conductive layer is not between the gate electrode and a top surface of the dummy nanosheet.
5 . The semiconductor device of claim 1 , wherein the first conductive layer is between the gate electrode and a top surface of the separation layer.
6 . The semiconductor device of claim 1 , wherein a width, in the second horizontal direction, of the first conductive layer is less than a width, in the second horizontal direction, of the plurality of upper nanosheets.
7 . The semiconductor device of claim 1 , wherein the gate electrode includes a lower gate electrode surrounding the plurality of lower nanosheets on the active pattern, and an upper gate electrode spaced apart from the lower gate electrode in the vertical direction and surrounding the plurality of upper nanosheets.
8 . The semiconductor device of claim 1 , further comprising: a second conductive layer between the gate electrode and the plurality of lower nanosheets, the second conductive layer not between the gate electrode and the plurality of upper nanosheets.
9 . The semiconductor device of claim 8 , further comprising: a third conductive layer between the gate electrode and the first conductive layer, the third conductive layer not between the gate electrode and the sidewalls in the second horizontal direction of each of the plurality of upper nanosheets.
10 . The semiconductor device of claim 1 , further comprising: a second conductive layer between the gate electrode and the plurality of lower nanosheets and between the gate electrode and the plurality of upper nanosheets, wherein the first conductive layer is between the plurality of upper nanosheets and the second conductive layer.
11 . The semiconductor device of claim 1 , further comprising: a gate insulating layer between the gate electrode and each of the plurality of lower nanosheets, the separation layer, and the plurality of upper nanosheets, wherein the first conductive layer is between the gate electrode and the gate insulating layer.
12 . The semiconductor device of claim 11 , wherein the gate insulating layer between the gate electrode and the plurality of lower nanosheets is in contact with the gate electrode.
13 . A semiconductor device comprising: an active pattern on a substrate and extending in a first horizontal direction; a plurality of lower nanosheets stacked on the active pattern to be spaced apart from one another in a vertical direction; a separation layer on the plurality of lower nanosheets; a plurality of upper nanosheets stacked on the separation layer to be spaced apart from one another in the vertical direction; a dummy nanosheet spaced apart from the plurality of upper nanosheets in the vertical direction, the dummy nanosheet including an insulating material; a gate electrode on the active pattern and extending in a second horizontal direction, which is different from the first horizontal direction, the gate electrode surrounding each of the plurality of lower nanosheets, the separation layer, the plurality of upper nanosheets, and the dummy nanosheet; and a first conductive layer disposed between the gate electrode and each of a top surface and a bottom surface of the plurality of upper nanosheets, the first conductive layer not between the gate electrode and the plurality of lower nanosheets.
14 . The semiconductor device of claim 13 , wherein sidewalls of the dummy nanosheet in the second horizontal direction are aligned in the vertical direction with sidewalls of the plurality of upper nanosheets in the second horizontal direction.
15 . The semiconductor device of claim 13 , wherein the first conductive layer is between the gate electrode and a bottom surface of the dummy nanosheet, the first conductive layer is not between the gate electrode and a top surface of the dummy nanosheet.
16 . The semiconductor device of claim 13 , wherein a width, in the second horizontal direction, of the first conductive layer is less than a width, in the second horizontal direction, of the plurality of upper nanosheets.
17 . The semiconductor device of claim 13 , further comprising: a second conductive layer between the gate electrode and the plurality of lower nanosheets, the second conductive layer not between the gate electrode and the plurality of upper nanosheets.
18 . The semiconductor device of claim 13 , further comprising: a second conductive layer between the gate electrode and the plurality of lower nanosheets, between the gate electrode and sidewalls in the second horizontal direction of the plurality of upper nanosheets, and between the gate electrode and the first conductive layer.
19 . The semiconductor device of claim 18 , further comprising: a third conductive layer between the gate electrode and the second conductive layer on each of the top surface and the bottom surface of the plurality of upper nanosheets, the third conductive layer not between the gate electrode and the sidewalls in the second horizontal direction of the plurality of upper nanosheets.
20 . A semiconductor device comprising: an active pattern extending in a first horizontal direction on a substrate; a plurality of lower nanosheets stacked on the active pattern to be spaced apart from one another in a vertical direction; a separation layer on the plurality of lower nanosheets; a plurality of upper nanosheets stacked on the separation layer to be spaced apart from one another in the vertical direction; a dummy nanosheet spaced apart from the plurality of upper nanosheets in the vertical direction, the dummy nanosheet includes an insulating material; a gate insulating layer along surfaces of the plurality of lower nanosheets, the separation layer, the plurality of upper nanosheets, and the dummy nanosheet; a gate electrode on the active pattern and extending in a second horizontal direction, which is different from the first horizontal direction, the gate electrode surrounding the plurality of lower nanosheets, the separation layer, the plurality of upper nanosheets, and the dummy nanosheet; and a conductive layer between the gate electrode and the gate insulating layer, wherein the conductive layer is between the gate electrode and a top surface of the separation layer, between the gate electrode and each of a top surface and a bottom surface of the plurality of upper nanosheets, and between the gate electrode and a bottom surface of the dummy nanosheet, the conductive layer is not between the gate electrode and sidewalls in the second horizontal direction of the separation layer, between the gate electrode and sidewalls in the second horizontal direction of the plurality of upper nanosheets, between the gate electrode and each of a top surface and sidewalls in the second horizontal direction of the dummy nanosheet, between the gate electrode and a bottom surface of the separation layer, and between the gate electrode and the plurality of lower nanosheets, and a width, in the second horizontal direction, of the conductive layer is less than a width, in the second horizontal direction, of the plurality of upper nanosheets.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims priority from Korean Patent Application No. 10-2022-0117258 filed on Sep. 16, 2022 in the Korean Intellectual Property Office, and all the benefits accruing therefrom under 35 U.S.C. 119, the contents of which in its entirety are herein incorporated by reference. BACKGROUND 1. Various example embodiments relate to a semiconductor device, and particularly, to a semiconductor device including a Multi-Bridge Channel Field Effect Transistor (MBCFET™). 2. As a scaling technique for increasing the density of an integrated circuit (IC) device, a multi-gate transistor has been suggested in which a fin- or nanowire-type silicon body is formed on a substrate and a gate is formed on the surface of the silicon body. Since the multi-gate transistor uses a three-dimensional (3D) channel, scaling may be facilitated or more easily managed. Alternatively or additionally, current control capability may be improved without increasing the length of the gate of the multi-gate transistor. Alternatively or additionally, a short channel effect (SCE), i.e., the phenomenon of the potential of a channel region being affected by a drain voltage, may be improved, e.g. may be reduced or effectively suppressed. SUMMARY Various example embodiments provide a device capable of controlling a threshold voltage in various manners by having or forming conductive films on the surface of a plurality of upper nanosheets, but not on the surface of a plurality of lower nanosheets, in a structure where the plurality of upper nano sheets are stacked on the plurality of lower nano sheets. However, features of example are not restricted to those set forth herein. The above and other aspects will become more apparent to one of ordinary skill in the art to which example embodiments pertains by referencing the detailed description of the present disclosure given below. According to various example embodiments, there is provided a semiconductor device, comprising an active pattern on a substrate and extending in a first horizontal direction, a plurality of lower nanosheets stacked on the active pattern to be spaced apart from one another in a vertical direction, a separation layer on the plurality of lower nanosheets, a plurality of upper nanosheets stacked on the separation layer to be spaced apart from one another in the vertical direction, a gate electrode extending on the active pattern in a second horizontal direction, which is different from the first horizontal direction. The gate electrode surrounds each of the plurality of lower nanosheets, the separation layer, and the plurality of upper nanosheets. The semiconductor device further comprises a first conductive layer between the gate electrode and each of a top surface and a bottom surface of the plurality of upper nanosheets, and the first conductive layer is not disposed between the gate electrode and sidewalls, in the second horizontal direction, of the plurality of upper nanosheets. According to various example embodiments, there is provided a semiconductor device, comprising an active pattern extending in a first horizontal direction on a substrate, a plurality of lower nanosheets stacked on the active pattern to be spaced apart from one another in a vertical direction, a separation layer on the plurality of lower nanosheets, a plurality of upper nanosheets stacked on the separation layer to be spaced apart from one another in the vertical direction, and a dummy nanosheet spaced apart from the plurality of upper nanosheets in the vertical direction. The dummy nanosheet includes an insulating material, a gate electrode extending on the active pattern in a second horizontal direction, which is different from the first horizontal direction, and the gate electrode surrounds each of the plurality of lower nanosheets, the separation layer, the plurality of upper nanosheets, and the dummy nanosheet. The semiconductor device comprises a first conductive layer between the gate electrode and each of a top surface and a bottom surface of the plurality of upper nanosheets, the first conductive layer is not disposed between the gate electrode and the plurality of lower nanosheets. According to various example embodiments, there is provided a semiconductor device, comprising an active pattern extending in a first horizontal direction on a substrate, a plurality of lower nanosheets stacked on the active pattern to be spaced apart from one another in a vertical direction, a separation layer on the plurality of lower nanosheets, a plurality of upper nanosheets stacked on the separation layer to be spaced apart from one another in the vertical direction, and a dummy nanosheet spaced apart from the plurality of upper nanosheets in the vertical direction. The dummy nanosheet includes an insulating material, a gate insulating layer along surfaces of the plurality of lower nanosheets, the separation layer, the plurality of upper nanosheets and the dummy