US-12622050-B2 - Integrated circuit and manufacturing method thereof

Abstract

An integrated circuit includes a plurality of transistors and a vertical local interconnection. The transistors include a plurality of gate components, a plurality of front-side source/drain epitaxies and a plurality of back-side source/drain epitaxies, wherein the front-side source/drain epitaxies are closer to a front-side of the integrated circuit than the back-side source/drain epitaxies. The vertical local interconnection connects a first connected-one of the front-side source/drain epitaxies with a second connected-one of the back-side source/drain epitaxies. A covered-one of the gate components is located between the first connected-one and the second connected-one, the covered-one comprises an front-side portion, a back-side portion and a covered portion connecting the front-side portion with the back-side portion, and the vertical local interconnection crosses the covered portion and exposes the front-side portion and the back-side portion.

Inventors

• Meng-Yu Lin
• Chun-Fu CHENG
• Hsiang-Hung Huang

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date

20260505

Application Date

20230120

Claims (20)

1. 1 . An integrated circuit, comprising: a plurality of transistors comprising a plurality of gate components, a plurality of front-side source/drain epitaxies and a plurality of back-side source/drain epitaxies, wherein the front-side source/drain epitaxies are closer to a front-side side of the integrated circuit than the back-side source/drain epitaxies; and a vertical local interconnection connecting a first connected-one of the front-side source/drain epitaxies with a second connected-one of the back-side source/drain epitaxies; wherein a covered-one of the gate components is located between the first connected-one and the second connected-one, the covered-one comprises an front-side portion, a back-side portion and a covered portion connecting the front-side portion with the back-side portion, and the vertical local interconnection crosses the covered portion and exposes the front-side portion and the back-side portion; wherein the vertical local interconnection comprises a first notch, a first lateral surface and a second lateral surface opposite to the first lateral surface, and the first notch extends toward a first-one of the first lateral surface and the second lateral surface from a second-one of the first lateral surface and the second lateral surface.
2. 2 . The integrated circuit as claimed in claim 1 , wherein the first connected-one and the second connected-one are drain epitaxies.
3. 3 . The integrated circuit as claimed in claim 1 , wherein the vertical local interconnection connects the first connected-one and the second connected-one in parallel.
4. 4 . The integrated circuit as claimed in claim 1 , wherein the transistors comprise a N-type Metal-Oxide-Semiconductors (NMOS) and a P-type Metal-Oxide- Semiconductors (PMOS), the NMOS and the PMOS share the first connected-one, and the first connected-one is drain epitaxy.
5. 5 . The integrated circuit as claimed in claim 1 , wherein the transistors comprise a NMOS and a PMOS, the NMOS and the PMOS share the second connected-one, and the second connected-one is drain epitaxy.
6. 6 . The integrated circuit as claimed in claim 1 , wherein the vertical local interconnection is shaped as a Z-shape.
7. 7 . The integrated circuit as claimed in claim 1 , wherein the vertical local interconnection further comprising a second notch, and the second notch extends toward the second-one of the first lateral surface and the second lateral surface from the first-one of the first lateral surface and the second lateral surface.
8. 8 . The integrated circuit as claimed in claim 1 , wherein the vertical local interconnection further comprises a front-side surface and a back-side surface opposite to the front-side surface, and the first notch extends toward a third-one of the front-side surface and the back-side surface from a fourth-one of the front-side surface and the back-side surface.
9. 9 . The integrated circuit as claimed in claim 8 , wherein the vertical local interconnection further comprising a second notch, and the second notch extends toward the fourth-one of the front-side surface and the back-side surface from the third-one of the front-side surface and the back-side surface.
10. 10 . An integrated circuit, comprising: a plurality of transistors comprising a plurality of front-side source/drain epitaxies and a plurality of back-side source/drain epitaxies, wherein the front-side source/drain epitaxies are closer to a front-side of the integrated circuit than the back-side source/drain epitaxies; and a vertical local interconnection connecting a first connected-one of the front-side source/drain epitaxies and a second connected-one of the back-side source/drain epitaxies; wherein the vertical local interconnection has a width less than a contacted poly pitch (CPP); wherein the vertical local interconnection comprises a first notch, a first lateral surface and a second lateral surface opposite to the first lateral surface, and the first notch extends toward a first-one of the first lateral surface and the second lateral surface from a second-one of the first lateral surface and the second lateral surface.
11. 11 . The integrated circuit as claimed in claim 10 , wherein the vertical local interconnection extends in single straight line.
12. 12 . The integrated circuit as claimed in claim 10 , wherein the first connected- one and the second connected-one are opposite to each other.
13. 13 . The integrated circuit as claimed in claim 10 , further comprising: a first dielectric sidewall; and a second dielectric sidewall; wherein the vertical local interconnection is formed between the first dielectric sidewall and the second dielectric sidewall.
14. 14 . The integrated circuit as claimed in claim 10 , further comprising: a cut metal gate on which the vertical local interconnection is formed.
15. 15 . The integrated circuit as claimed in claim 10 , wherein the vertical local interconnection further comprises a second notch, and the second notch extends toward the second-one of the first lateral surface and the second lateral surface from the first-one of the first lateral surface and the second lateral surface.
16. 16 . The integrated circuit as claimed in claim 10 , wherein the vertical local interconnection further comprises a front-side surface and a back-side surface opposite to the front-side surface, and the first notch extends toward a third-one of the front-side surface and the back-side surface from a fourth-one of the front-side surface and the back-side surface.
17. 17 . A manufacturing method of an integrated circuit, comprising: forming a plurality of transistors comprising a plurality of gate components, a plurality of front-side source/drain epitaxies and a plurality of back-side source/drain epitaxies, wherein the front-side source/drain epitaxies are closer to a front-side side of the integrated circuit than the back-side source/drain epitaxies; and forming a vertical local interconnection connecting a first connected-one of the front-side source/drain epitaxies with a second connected-one of the back-side source/drain epitaxies, wherein a covered-one of the gate components is located between the first connected-one and the second connected-one, the covered-one comprises an front-side portion, a back-side portion and a covered portion connecting the front-side portion with the back-side portion, and the vertical local interconnection crosses the covered portion and exposes the front-side portion and the back-side portion; wherein the manufacturing method further comprises: forming a first notch on a vertical local interconnection material which is formed in the integrated circuit from the front-side; and forming a second notch on the vertical local interconnection material from a back-side of the integrated circuit.
18. 18 . The manufacturing method as claimed in claim 17 , further comprising: forming a recess on a dielectric layer; and forming the vertical local interconnection material within the recess.
19. 19 . The manufacturing method as claimed in claim 18 , wherein the vertical local interconnection material has a first lateral surface, a second lateral surface opposite to the first lateral surface, a front-side surface and a back-side surface opposite to the front-side surface; the manufacturing method further comprising: wherein the first notch extends toward a first-one of the first lateral surface and the second lateral surface from a second-one of the first lateral surface and the second lateral surface, and extends toward a third-one of the front-side surface and the back-side surface from a fourth-one of the front-side surface and the back-side surface.
20. 20 . The manufacturing method as claimed in claim 19 , further comprising: wherein the second notch extends toward the second-one of the first lateral surface and the second lateral surface from the first-one of the first lateral surface and the second lateral surface, and extends toward the fourth-one of the front-side surface and the back-side surface from the third-one of the front-side surface and the back-side surface.

Description

PRIORITY CLAIM AND CROSS-REFERENCE This application claims the benefit of U.S. provisional application Ser. No. 63/430,439, filed Dec. 6, 2022, the subject matter of which is incorporated herein by reference. BACKGROUND An integrated circuit is an electronic component that utilizes the electronic properties of semiconductor materials to affect electrons or their associated fields. One widely used type of integrated circuit is the field-effect transistor (FET). However, parasitic impedance may exist in these semiconductor materials and it will negatively affect the performance of the integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 illustrates a schematic diagram of an integrated circuit according to an embodiment of the present disclosure; FIG. 2 illustrates a schematic diagram of a view of the vertical local interconnection of FIG. 1 in +Y axis; FIG. 3 illustrates an equivalent circuit diagram of the integrated circuit of FIG. 1; FIG. 4 illustrates a schematic diagram of a top view of the integrated circuit of FIG. 1; FIG. 5 illustrates a schematic diagram of a cross-sectional view of the integrated circuit of FIG. 1 in a direction 5-5′; FIG. 6 illustrates a schematic diagram of a cross-sectional view of the integrated circuit of FIG. 1 in a direction 6-6′; FIG. 7 illustrates a schematic diagram of a cross-sectional view of the integrated circuit of FIG. 1 in a direction 7-7′; FIG. 8 illustrates a schematic diagram of a cross-sectional view of the integrated circuit of FIG. 1 in a direction 8-8′; FIG. 9 illustrates a schematic diagram of an integrated circuit according to an embodiment of the present disclosure; FIG. 10 illustrates a schematic diagram of a cross-sectional view of the integrated circuit of FIG. 9 in a direction 10-10; FIG. 11 illustrates a schematic diagram of a cross-sectional view of the integrated circuit of FIG. 9 in a direction 11-11′; FIG. 12A illustrates a schematic diagram of a dielectric layer formed within an integrated circuit; FIG. 12B illustrates a schematic diagram of the integrated circuit of FIG. 12A in a direction 8B-8B′; FIG. 13A illustrates a schematic diagram of forming a recess on the dielectric layer of FIG. 13A; FIG. 13B illustrates a schematic diagram of the integrated circuit of FIG. 13A in a direction 13B-13B′; FIG. 14A illustrates a schematic diagram of forming a vertical local interconnection material within the recess; FIG. 14B illustrates a schematic diagram of the integrated circuit of FIG. 14A in a direction 14B-14B′; FIG. 15A illustrates a schematic diagram of forming a photoresist on the integrated circuit of FIG. 14A; FIG. 15B illustrates a schematic diagram of the integrated circuit of FIG. 15A in a direction 15B-15B′; FIG. 16A illustrates a schematic diagram of forming a first notch on the vertical local interconnection; FIG. 16B illustrates a schematic diagram of the integrated circuit of FIG. 16A in a direction 16B-16B′; FIG. 17 illustrates a schematic diagram of removing the photoresist; FIG. 18A illustrates a schematic diagram of flipping the integrated circuit of FIG. 17; FIG. 18B illustrates a schematic diagram of the integrated circuit of FIG. 18A in a direction 18B-18B′; FIG. 19 illustrates a schematic diagram of forming a photoresist on the integrated circuit of FIG. 18A; FIG. 20A illustrates a schematic diagram of forming a second notch on the vertical local interconnection; FIG. 20B illustrates a schematic diagram of the integrated circuit of FIG. 20A in a direction 20B-20B′; FIG. 21 illustrates a schematic diagram of removing the photoresist; FIG. 22 illustrates a schematic diagram of removing the insulation layer; FIG. 23A illustrates a cross-sectional view, viewed in a direction 10-10 of FIG. 9, of a recess for the cut metal gate being formed; FIG. 23B illustrates a cross-sectional view, viewed in a direction 11-11 of FIG. 9; FIG. 24A illustrates a cross-sectional view, viewed in a direction 10-10 of FIG. 9, of the first dielectric sidewall 271 and the second dielectric sidewall being formed; FIG. 24B illustrates a cross-sectional view, viewed in a direction 11-11 of FIG. 9; FIG. 25A illustrates a cross-sectional view, viewed in a direction 10-10 of FIG. 9, of a vertical local interconnection material being formed; FIG. 25B illustrates a cross-sectional view, viewed in a direction 11-11 of FIG. 9; FIG. 26A illustrates a cross-sectional view, viewed in a direction 10-10 of FIG. 9, of a portion of the vertical local interconnection material being removed; FIG. 26B illustrates a cross-sectional view, viewed in a direction 11-11 of FIG. 9, of a portion of the vertical loca