US-12622051-B2 - Field effect transistor high aspect ratio patterning

Abstract

A semiconductor device integrated circuit includes a semiconductor wafer, an insulator on the wafer, a first field effect transistor (FET) positioned in the insulator, a second FET positioned in the insulator between the wafer and the first FET, a pore in the insulator that extends to the second FET, a via that is electrically connected to the second FET and positioned in the pore, and a liner positioned between the via and the pore. The first FET is electrically insulated from the via by the liner.

Inventors

• Domingo Ferrer
• Wai Kin Li

Assignees

• INTERNATIONAL BUSINESS MACHINES CORPORATION

Dates

Publication Date

20260505

Application Date

20230330

Claims (10)

1. 1 . A semiconductor device comprising: a semiconductor wafer; an insulator on the semiconductor wafer; a first field effect transistor (FET) positioned in the insulator; a second FET positioned in the insulator between the semiconductor wafer and the first FET; a pore in the insulator that extends to and directly contacts the second FET; a liner positioned within a top portion of the pore; and a via that is positioned through the pore in direct contact with the liner at the top portion of the pore and in direct contact with the insulator at a bottom portion of the pore, wherein the first FET is electrically insulated from the via by the insulator and the liner.
2. 2 . The semiconductor device of claim 1 , wherein the liner is comprised of a low dielectric constant material.
3. 3 . The semiconductor device of claim 1 , wherein the liner extends part way along the pore towards the second FET.
4. 4 . The semiconductor device of claim 3 , wherein the liner extends past the first FET as it extends along the pore towards the second FET.
5. 5 . The semiconductor device of claim 1 , wherein the via is L-shaped.
6. 6 . The semiconductor device of claim 1 , wherein the via is shaped as a solid of revolution of an L-shape that is intersected by the second FET.
7. 7 . The semiconductor device of claim 1 , wherein the second FET is a nanosheet n-channel FET (NFET), and the first FET is a nanosheet p-channel FET (PFET).
8. 8 . The semiconductor device of claim 1 , wherein the insulator has a higher dielectric constant than the liner.
9. 9 . The semiconductor device of claim 1 , wherein the liner is an air gap.
10. 10 . A semiconductor device comprising: a semiconductor wafer; an insulator on the semiconductor wafer; a first nanosheet field effect transistor (FET) positioned in the insulator; a second nanosheet FET positioned in the insulator between the semiconductor wafer and the first nanosheet FET; a pore in the insulator that extends to a source/drain region of the second nanosheet FET; a liner positioned within a top portion of the pore, wherein the liner is comprised of a low dielectric constant material and is shorter than the pore; and a via connected to the source/drain region of the second nanosheet FET and positioned through the pore in direct contact with the liner at the top portion of the pore and in direct contact with the insulator at a bottom portion of the pore.

Description

BACKGROUND The present invention relates to semiconductor devices, and more specifically, to vias between layers in an integrated circuit. Field-effect transistors (FETs) use an electric field effect to control current flow within a semiconductor. Specifically, FETs may use the electric charge of their gates to affect and control the current flow through a channel. One common type of FET is a finFET. FinFETs, as referred to herein, may be FETs in a vertical fin shape. FinFETs may have vertically stacked channels, and vertically stacked components in general, in order to form the tall, narrow fin shape of a finFET. Another type of FET is a nanosheet transistor, also referred to herein as a nanosheet FET. Nanosheet transistors may include horizontally stacked nanosheets, instead of the thin vertical fin of a FinFET. Each nanosheet may act as a channel, therefore nanosheet transistors may include a plurality of channels for current to flow. FETs may have two typical configurations, N-channel FETs (NFETs) and P-channel FETs (PFETs). NFETs introduce (for example, through doping) an n-type impurity to the semiconductor material of the channel between the source and the drain, and PFETs introduce a p-type impurity to the semiconductor material of the channel. These two types of FETs can be employed in either fin configurations or nanosheet configurations. SUMMARY A semiconductor device integrated circuit includes a semiconductor wafer, an insulator on the wafer, a first field effect transistor (FET) positioned in the insulator, a second FET positioned in the insulator between the wafer and the first FET, a pore in the insulator that extends to the second FET, a via that is electrically connected to the second FET and positioned in the pore, and a liner positioned between the via and the pore. The first FET is electrically insulated from the via by the liner. A method of manufacturing a semiconductor device includes forming a pore in an insulator alongside a first field effect transistor (FET), forming a liner in the pore, removing a bottom of the liner, extending the pore using an anisotropic removal process to expose a second FET, and extending the pore using another removal process to widen a portion of the pore the is below the liner and over the second FET. A semiconductor device integrated circuit includes a semiconductor wafer, an insulator on the wafer, a first nanosheet field effect transistor (FET) positioned in the insulator, a second nanosheet FET positioned in the insulator between the wafer and the first nanosheet FET, a pore in the insulator that extends to a source/drain region of the second nanosheet FET, a liner positioned in the pore, wherein the liner is comprised of a low dielectric constant material and is shorter than the pore, and a via connected to the source/drain region of the second nanosheet FET and positioned in the pore and the liner. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-section front view of an integrated circuit (IC) chip stack, in accordance with embodiments of the present disclosure. FIG. 2 is a cross-section front view of an IC chip stack, in accordance with an embodiment of the present disclosure. FIG. 3 is a flowchart of a method of manufacturing the IC chip stack of FIG. 2, in accordance with an embodiment of the present disclosure. FIGS. 4A-4G are a series of cross-section views of the method of FIG. 3 of manufacturing the IC chip stack of FIG. 2, in accordance with an embodiment of the present disclosure. FIG. 5 is a cross-section front view of an alternative IC chip stack, in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION Various embodiments of the present disclosure are described herein with reference to the related drawings. Alternative embodiments can be devised without departing from the scope of the present disclosure. It is noted that various connections and positional relationships (e.g., over, below, adjacent, etc.) are set forth between elements in the following description and in the drawings. These connections and/or positional relationships, unless specified otherwise, can be direct or indirect, and the present disclosure is not intended to be limiting in this respect. Accordingly, a coupling of entities can refer to either a direct or an indirect coupling, and a positional relationship between entities can be a direct or indirect positional relationship. As an example of an indirect positional relationship, references in the present description to forming layer “A” over layer “B” include situations in which one or more intermediate layers (e.g., layers “C” and “D”) are between layer “A” and layer “B” as long as the relevant characteristics and functionalities of layer “A” and layer “B” are not substantially changed by the intermediate layer(s). The following definitions and abbreviations are to be used for the interpretation of the claims and the specification. As used herein, the terms “comprises,” “comprising,” “i