US-12622052-B2 - Integrated circuit structures having cut metal gates

Abstract

Integrated circuit structures having cut metal gates, and methods of fabricating integrated circuit structures having cut metal gates, are described. For example, an integrated circuit structure includes a fin having a portion protruding above a shallow trench isolation (STI) structure. A gate dielectric material layer is over the protruding portion of the fin and over the STI structure. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate plug is laterally spaced apart from the fin, the dielectric gate plug on but not through the STI structure. The gate dielectric material layer and the conductive gate layer are not along sides of the dielectric gate plug, and the conductive gate fill material is in contact with the sides of the dielectric gate plug.

Inventors

• Tahir Ghani
• Mohit K. HARAN
• Mohammad Hasan
• Biswajeet Guha
• Alison V. DAVIS
• Leonard P. GULER

Assignees

• INTEL CORPORATION

Dates

Publication Date

20260505

Application Date

20210607

Claims (10)

1. 1 . An integrated circuit structure, comprising: a fin having a portion protruding above a shallow trench isolation (STI) structure; a gate dielectric material layer over the protruding portion of the fin and over the STI structure; a conductive gate layer over the gate dielectric material layer; a conductive gate fill material over the conductive gate layer; and a dielectric gate plug laterally spaced apart from the fin, the dielectric gate plug having an uppermost surface above an uppermost surface of the conductive gate fill material, wherein the gate dielectric material layer and the conductive gate layer are not along sides of the dielectric gate plug, and wherein the conductive gate fill material is in contact with the sides of the dielectric gate plug.
2. 2 . The integrated circuit structure of claim 1 , wherein the gate dielectric material layer is a high-k gate dielectric layer.
3. 3 . The integrated circuit structure of claim 1 , wherein the conductive gate layer is a workfunction metal layer.
4. 4 . The integrated circuit structure of claim 1 , wherein a dielectric gate cap is on the conductive gate fill material.
5. 5 . The integrated circuit structure of claim 1 , wherein an oxidized portion of the fin is between the protruding portion of the fin and the gate dielectric material layer.
6. 6 . A computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure, comprising: a fin having a portion protruding above a shallow trench isolation (STI) structure; a gate dielectric material layer over the protruding portion of the fin and over the STI structure; a conductive gate layer over the gate dielectric material layer; a conductive gate fill material over the conductive gate layer; and a dielectric gate plug laterally spaced apart from the fin, the dielectric gate plug having an uppermost surface above an uppermost surface of the conductive gate fill material, wherein the gate dielectric material layer and the conductive gate layer are not along sides of the dielectric gate plug, and wherein the conductive gate fill material is in contact with the sides of the dielectric gate plug.
7. 7 . The computing device of claim 6 , further comprising: a memory coupled to the board.
8. 8 . The computing device of claim 6 , further comprising: a communication chip coupled to the board.
9. 9 . The computing device of claim 6 , wherein the component is a packaged integrated circuit die.
10. 10 . The computing device of claim 6 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

Description

TECHNICAL FIELD Embodiments of the disclosure are in the field of integrated circuit structures and processing and, in particular, integrated circuit structures having cut metal gates and methods of fabricating integrated circuit structures having cut metal gates. BACKGROUND For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant. In the manufacture of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, have become more prevalent as device dimensions continue to scale down. In conventional processes, tri-gate transistors are generally fabricated on either bulk silicon substrates or silicon-on-insulator substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and because they enable a less complicated tri-gate fabrication process. In another aspect, maintaining mobility improvement and short channel control as microelectronic device dimensions scale below the 10 nanometer (nm) node provides a challenge in device fabrication. Nanowires used to fabricate devices provide improved short channel control. Scaling multi-gate and nanowire transistors has not been without consequence, however. As the dimensions of these fundamental building blocks of microelectronic circuitry are reduced and as the sheer number of fundamental building blocks fabricated in a given region is increased, the constraints on the lithographic processes used to pattern these building blocks have become overwhelming. In particular, there may be a trade-off between the smallest dimension of a feature patterned in a semiconductor stack (the critical dimension) and the spacing between such features. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A illustrates a cross-sectional view of an integrated circuit structure having a fin and a pre-metal gate dielectric plug. FIG. 1B illustrates a cross-sectional view of an integrated circuit structure having a fin and a cut metal gate dielectric plug, in accordance with an embodiment of the present disclosure. FIG. 2A illustrates a cross-sectional view of an integrated circuit structure having a fin and a pre-metal gate dielectric plug. FIG. 2B illustrates a cross-sectional view of an integrated circuit structure having a fin and a cut metal gate dielectric plug, in accordance with an embodiment of the present disclosure. FIG. 3A illustrates a cross-sectional view of an integrated circuit structure having nanowires and a pre-metal gate dielectric plug. FIG. 3B illustrates a cross-sectional view of an integrated circuit structure having nanowires and a cut metal gate dielectric plug, in accordance with an embodiment of the present disclosure. FIG. 4A illustrates a cross-sectional view of an integrated circuit structure having nanowires and a pre-metal gate dielectric plug. FIG. 4B illustrates a cross-sectional view of an integrated circuit structure having nanowires and a cut metal gate dielectric plug, in accordance with an embodiment of the present disclosure. FIGS. 5A-5C illustrate plan views of comparative integrated circuit structures, in accordance with an embodiment of the present disclosure. FIGS. 6A-6C illustrate cross-sectional views of comparative integrated circuit structures, in accordance with an embodiment of the present disclosure. FIGS. 7A-7J illustrates cross-sectional views of various operations in a method of fabricating a gate-all-around integrated circuit structure, in accordance with an embodiment of the present disclosure. FIG. 8 illustrates a cross-sectional view of a non-planar integrated circuit structure as taken along a gate line, in accordance with an embodiment of the present disclosure. FIG. 9 illustrates cross-sectional views taken through nanowires and fins for a non-endcap architecture (left-hand side (a)) versus a self-aligned gate endcap (SAGE) architecture (right-hand side (b)), in accordance with an embodiment of the present disclosure. FIG. 10 illustrates cross-sectional views representing various operations in a method of fabricating a self-aligned gate endcap (SAGE) structure with gate-all-around devices, in accordance with an embodiment of the present disclosure. FIG. 11A illustrates a three-dimensional cross-sectional view of a nanowire-based integrated circuit structure, in accordance with an embodiment of the present disclosure. FIG. 11B illustrates a cross-sectional source or drain view of the nanowire-based integrated circuit struc