US-12622053-B2 - Hybrid CMOS with fin and nanosheet architectures

Abstract

A hybrid semiconductor structure, a system, and a method of forming a hybrid semiconductor structure. The hybrid semiconductor structure may include a PFET region, where the PFET region includes a first channel in a fin shape; an NFET region, where the NFET region includes a second channel, the second channel including a nanosheet; and an isolation bar separating the PFET region from the NFET region. The system may include a hybrid semiconductor structure including a PFET region; an NFET region; an isolation bar separating the PFET and NFET region; and a gate surrounding a plurality of sidewalls of the first channel and the second channel. The method may include forming an isolation bar between a first channel material in an NFET region and a second channel material in a PFET region; forming the second channel material into a fin shape; and forming the first channel material into stacked nanosheets.

Inventors

• Ruilong Xie
• Alexander Reznicek
• Daniel Schmidt
• Tsung-Sheng KANG

Assignees

• INTERNATIONAL BUSINESS MACHINES CORPORATION

Dates

Publication Date

20260505

Application Date

20221228

Claims (20)

1. 1 . A hybrid semiconductor structure, wherein the hybrid semiconductor structure comprises: a PFET region, wherein the PFET region comprises a first channel in a vertically oriented fin shape; an NFET region, wherein the NFET region comprises a second channel, the second channel comprising a horizontally oriented nanosheet; a shallow trench isolation (STI) region disposed below and between the PFET region and the NFET region; and an isolation bar separating the PFET region from the NFET region and extending at least one of the first channel and the second channel and extending below the STI region.
2. 2 . The hybrid semiconductor structure of claim 1 , wherein the isolation bar is connected to the second channel.
3. 3 . The hybrid semiconductor structure of claim 2 , wherein the isolation bar is further connected to a substrate, wherein the substrate is below the PFET region and the NFET region.
4. 4 . The hybrid semiconductor structure of claim 1 , wherein the PFET region may be between 20 nanometers and 40 nanometers from the NFET region.
5. 5 . The hybrid semiconductor structure of claim 1 , further comprising: a shallow trench isolation (STI) region below and between the PFET region and the NFET region.
6. 6 . The hybrid semiconductor structure of claim 1 , wherein the isolation bar comprises at least one of SIN, SiOCN, SiBCN, SiOC, and SiC.
7. 7 . The hybrid semiconductor structure of claim 1 , where the PFET region further comprises a third channel.
8. 8 . A system, wherein the system comprises: a hybrid semiconductor structure, the hybrid semiconductor structure comprising: a PFET region, wherein the PFET region comprises a first channel in a fin shape; an NFET region, wherein the NFET region comprises a second channel, the second channel comprising a nanosheet; an isolation bar separating the PFET region from the NFET region and extending above and below both the first channel and the second channel, the isolation bar directly connected to a sidewall of the nanosheet; and a gate surrounding a plurality of sidewalls of the first channel and the second channel.
9. 9 . The system of claim 8 , wherein the isolation bar is connected to the second channel.
10. 10 . The system of claim 8 , wherein the PFET region may be between 20 nanometers and 40 nanometers from the NFET region.
11. 11 . The system of claim 8 , wherein the hybrid semiconductor structure further comprises a substrate, wherein the substrate is below the PFET region and the NFET region.
12. 12 . The system of claim 11 , wherein the isolation bar is connected to the substrate.
13. 13 . The system of claim 12 , wherein the isolation bar extends above the first channel and the second channel.
14. 14 . The system of claim 8 , wherein the isolation bar comprises at least one of SiN, SiOCN, SiBCN, SiOC, and SiC.
15. 15 . A hybrid semiconductor structure comprising: a first region; a second region; a shallow trench isolation (STI) region below and between the first region and the second region; a first transistor within the first region and comprising a vertically orientated fin channel; a second transistor within the second region and comprising a horizontally orientated nanosheet channel; and an isolation bar separating the vertically orientated fin channel and the horizontally orientated nanosheet channel and extending above at least one of the vertically orientated fin channel and horizontally orientated nanosheet channel and extending below the STI region.
16. 16 . The hybrid semiconductor structure of claim 15 , wherein a sidewall of the horizontally orientated nanosheet channel is directly connected to the isolation bar.
17. 17 . The hybrid semiconductor structure of claim 16 , wherein the isolation bar is further directly connected to a substrate, wherein the substrate is below the first transistor and below the second transistor.
18. 18 . The hybrid semiconductor structure of claim 15 , wherein a top surface of the isolation bar is above respective top surfaces of the vertically orientated fin channel and the horizontally orientated nanosheet channel.
19. 19 . The hybrid semiconductor structure of claim 15 , wherein a top surface of the vertically orientated fin channel and a top surface of the horizontally orientated nanosheet channel are substantially coplanar.
20. 20 . The hybrid semiconductor structure of claim 17 , further comprising: a first bottom dielectric isolation (BDI) region upon the substrate aligned with the vertically orientated fin channel; and a second bottom BDI region upon the substrate aligned with the horizontally orientated nanosheet channel.

Description

BACKGROUND The present disclosure relates to semiconductors and transistors and, more specifically, to hybrid fin and nanosheet architectures within the semiconductor. Semiconductors, such as complementary metal-oxide-semiconductors (CMOS), are commonly used in computer chips and computer technology. These semiconductor chips/devices typically include transistor(s). Transistors are devices used to switch or amplify electric current or voltage. Field-effect transistors (FETs) use an electric field effect to control current flow within a semiconductor. FETs have three terminals—a source, a drain, and a gate. The source may introduce/provide current to the transistor, the drain may be the terminal that provides the output current, and the gate may be used to control the current flow from the source to the drain. Specifically, FETs may use the electric charge of their gates to affect and control the current flow through the channel. Current may flow using charge carriers that may be either electrons or holes. Electron charge carriers may be negatively charged particles (i.e., electrons) that carry charge and create an electric current. Hole charge carriers (referred to herein as holes) are positions on the FET channel that lack an electron (for instance, at positions of positive charge that is equal to the negative charge of an electron and/or positions where an electron could or should be). These holes may be positive charges, and they may move in an opposite direction of electrons, in some instances. The electric charge and/or voltage of the FET gates may be used to control the movements of the electrons and/or holes, which may then affect the current and charge being transmitted through the channel from the source to the drain. One common type of FET is a finFET. FinFETs, as referred to herein, may be FETs in a vertical fin shape. FinFETs may have vertically stacked channels, and vertically stacked components in general, in order to form the tall, narrow fin shape of a finFET. Another type of FET is a nanosheet transistor, also referred to herein as a nanosheet FET. Nanosheet transistors may include horizontally stacked nanosheets, instead of the thin vertical fin of an FET. Each nanosheet may act as a channel, therefore nanosheet transistors may include a plurality of channels for current to flow. Nanosheet transistors, like finFETs and other types of FETs, include a source, a drain, and a gate. In some instances, the gate in a nanosheet transistor may surround the channel portion (i.e., the stacked nanosheets) of the transistor, which allows the gate to surround all sides of the channel(s). This is different than a finFET, which has a gate that can surround up to three sides of the channel, but not the entire channel. SUMMARY The present invention provides a hybrid semiconductor, a system, and a method of forming a hybrid fin and nanosheet architecture within the semiconductor. The hybrid semiconductor structure may include a PFET region, where the PFET region includes a first channel in a fin shape. The hybrid semiconductor structure may also include an NFET region, where the NFET region includes a second channel, the second channel including a nanosheet. The hybrid semiconductor structure may also include an isolation bar separating the PFET region from the NFET region. The system may include a hybrid semiconductor structure. The hybrid semiconductor structure may include a PFET region, where the PFET region includes a first channel in a fin shape. The hybrid semiconductor structure may also include an NFET region, where the NFET region includes a second channel, the second channel including a nanosheet. The hybrid semiconductor structure may also include an isolation bar separating the PFET region from the NFET region. The hybrid semiconductor structure may also include a gate surrounding a plurality of sidewalls of the first channel and the second channel. The method may include forming an isolation bar between a first channel material in an NFET region and a second channel material in a PFET region. The method may also include forming the second channel material into a fin shape, resulting in a fin shaped channel in the PFET region. The method may also include forming the first channel material into stacked nanosheets, resulting in a stacked nanosheet channel in the NFET region. The above summary is not intended to describe each illustrated embodiment or every implementation of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS The drawings included in the present application are incorporated into, and form part of, the specification. They illustrate embodiments of the present disclosure and, along with the description, serve to explain the principles of the disclosure. The drawings are only illustrative of certain embodiments and do not limit the disclosure. FIG. 1 depicts a schematic diagram of an example hybrid semiconductor cell, according to some embodiments. FIG. 2A depicts a top down vie