US-12622054-B2 - Integration of multimodal transistors with transistor fabrication sequence

Abstract

A semiconductor device and fabrication method are described for integrating a nanosheet transistor with a multimodal transistor (MMT) in a single nanosheet process flow by processing a wafer substrate to form buried metal source/drain structures in an MMT region that are laterally spaced apart from one another and positioned below an MMT semiconductor channel layer before forming a transistor stack of alternating Si and SiGe layers in an FET region which are selectively processed to form gate electrode openings so that a first ALD oxide and metal layer are patterned and etched to form gate electrodes in the transistor stack and to form a channel control gate electrode over the MMT semiconductor channel layer, and so that a second oxide and conductive layer are patterned and etched to form a current control gate electrode over the MMT semiconductor channel layer and adjacent to the channel control gate electrode.

Inventors

• MARK DOUGLAS HALL
• Tushar Praful Merchant
• Maryfe Hernandez
• Anirban Roy

Assignees

• NXP USA, INC.

Dates

Publication Date

20260505

Application Date

20230911

Claims (20)

1. 1 . A method for forming a semiconductor device comprising: providing a wafer substrate comprising a field effect transistor region and a multimodal transistor (MMT) region; processing the wafer substrate to form metal source/drain structures in the MMT region that are laterally spaced apart from one another and positioned below an MMT semiconductor channel layer; processing the wafer substrate to form a transistor semiconductor channel in the field effect transistor region of the wafer substrate; sequentially depositing a first dielectric layer and a first conductive layer over the field effect transistor region and the MMT region; selectively etching the first conductive layer and the first dielectric layer to form a control electrode for the transistor semiconductor channel and to form a first MMT channel control electrode in the MMT region; depositing a second dielectric layer and a second conductive layer over at least the MMT region; and selectively etching the second conductive layer to form a second MMT current control electrode that is positioned adjacent to the first MMT channel control electrode to control current flow in the MMT semiconductor channel layer.
2. 2 . The method of claim 1 , where the first MMT channel control electrode, second MMT channel control electrode, MMT semiconductor channel layer, and metal source/drain structures form a multimodal transistor device.
3. 3 . The method of claim 1 , where the wafer substrate comprises a buried oxide substrate layer covered by an upper semiconductor layer.
4. 4 . The method of claim 1 , where the wafer substrate comprises a monocrystalline silicon substrate.
5. 5 . The method of claim 1 , where processing the wafer substrate to form metal source/drain structures comprises: selectively etching MMT source/drain openings through an upper semiconductor layer and into an underlying buried oxide layer in the MMT region; sequentially depositing an insulating liner layer, a barrier liner layer, and one or more metal layers to fill the MMT source/drain openings; polishing and/or recess etching the insulating liner layer, the barrier liner layer, and the one or more metal layers to form metal source/drain structures in the source/drain openings that are recessed below an upper surface of the upper semiconductor layer; epitaxially growing the MMT semiconductor channel layer from the upper semiconductor layer to bury the metal source/drain structures; and planarizing the MMT semiconductor channel layer with the upper surface of the upper semiconductor layer.
6. 6 . The method of claim 1 , where processing the wafer substrate to form the transistor semiconductor channel comprises: providing a stack of alternating first and second semiconductor layers on at least the field effect transistor region of the wafer substrate; selectively etching the stack of alternating first and second semiconductor layers to form a transistor stack on at least the field effect transistor region of the wafer substrate; and processing the transistor stack to selectively remove at least a portion of the first semiconductor layers, thereby forming control electrode openings between the second semiconductor layers which form the transistor semiconductor channel.
7. 7 . The method of claim 6 , where the first semiconductor layer comprises a silicon germanium nanosheet layer, and where the second semiconductor layer comprises a silicon nanosheet layer.
8. 8 . The method of claim 6 , where sequentially depositing the first dielectric layer and the first conductive layer comprises: depositing an atomic layer deposition (ALD) oxide layer over the field effect transistor region and the MMT region; and depositing an ALD metal layer over the ALD oxide layer in the field effect transistor region and the MMT region, thereby filling the control electrode openings with the ALD oxide layer and ALD metal layer.
9. 9 . The method of claim 8 , where selectively etching the first conductive layer and the first dielectric layer forms the control electrode from the ALD oxide layer and ALD metal layer in the control electrode openings which surround the transistor semiconductor channel in the transistor stack formed from the second semiconductor layers.
10. 10 . The method of claim 6 , where selectively etching the first conductive layer and the first dielectric layer forms the first MMT channel control electrode in the MMT region to be located over the MMT semiconductor channel layer and to be laterally positioned between the metal source/drain structures.
11. 11 . The method of claim 6 , where selectively etching the second conductive layer forms the second MMT channel control electrode in the MMT region to be located over the MMT semiconductor channel layer and to be laterally positioned in alignment with the metal source structure.
12. 12 . A method for forming a semiconductor device comprising: providing a substrate comprising an upper semiconductor layer formed over a buried oxide layer; forming metal source/drain structures in the substrate below the upper semiconductor layer; epitaxially growing a multimodal transistor (MMT) semiconductor channel layer from the upper semiconductor layer to cover the metal source/drain structures; forming a first insulator layer over at least the MMT semiconductor channel layer using a first conformal insulator atomic layer deposition (ALD) process; forming a first conductor layer over the first insulator layer using a first conformal conductor ALD process; selectively etching at least the first conductor layer to form a first MMT channel control electrode that is positioned over the MMT semiconductor channel layer to extend between the metal source/drain structures; forming a second insulator layer over at least the first MMT channel control electrode and exposed portions of the MMT semiconductor channel layer; forming a second conductor layer over the second insulator layer; selectively etching at least the second conductor layer to form a second MMT current control electrode that is positioned over the MMT semiconductor channel layer and adjacent to the first MMT channel control electrode to control current flow in the MMT semiconductor channel layer, where the second MMT current control electrode is insulated from the first MMT channel control electrode by the second insulator layer.
13. 13 . The method of claim 12 , where forming metal source/drain structures comprises: selectively etching MMT source/drain openings through the upper semiconductor layer and into the buried oxide layer; sequentially depositing an insulating liner layer, a barrier liner layer, and one or more metal layers to fill the MMT source/drain openings; and polishing and/or recess etching the insulating liner layer, the barrier liner layer, and the one or more metal layers to form metal source/drain structures in the source/drain openings that are recessed below an upper surface of the upper semiconductor layer.
14. 14 . The method of claim 12 , further comprising processing the substrate to form a transistor semiconductor channel in a field effect transistor region of the substrate after epitaxially growing the MMT semiconductor channel layer and before forming the first insulator layer over at least the MMT semiconductor channel layer.
15. 15 . The method of claim 14 , where processing the substrate to form the transistor semiconductor channel comprises: providing a stack of alternating first and second semiconductor layers on at least a field effect transistor region of the substrate; selectively etching the stack of alternating first and second semiconductor layers to form a transistor stack on at least the field effect transistor region of the substrate; processing the transistor stack to form epitaxial semiconductor current terminal regions adjacent to the transistor stack; and processing the transistor stack to selectively remove at least a portion of the first semiconductor layers, thereby forming control electrode openings between the second semiconductor layers which form the transistor semiconductor channel that connects the epitaxial semiconductor current terminal regions.
16. 16 . The method of claim 15 , where the first conformal insulator ALD process and the first conformal conductor ALD process sequentially fill the control electrode openings with the first insulator layer and the first conductor layer.
17. 17 . The method of claim 16 , further comprising selectively etching the first insulator layer and the first conductor layer to form a gate control electrode for the transistor semiconductor channel in the field effect transistor region of the substrate.
18. 18 . The method of claim 12 , where the first MMT channel control electrode, second MMT channel control electrode, MMT semiconductor channel layer, and metal source/drain structures form a multimodal transistor device.
19. 19 . The method of claim 12 , where selectively etching at least the second conductor layer forms the second MMT current control electrode to be positioned over one of the metal source/drain structures.
20. 20 . A semiconductor device comprising: a substrate; a nanosheet transistor device comprising a nanosheet stack formed on top of the substrate between first and second epitaxial current terminal semiconductor regions, where the nanosheet stack comprises an all-around control electrode formed around semiconductor layers from the nanosheet stack which connect the first and second epitaxial current terminal semiconductor regions; and a multimodal transistor device integrated with the nanosheet transistor device on top of the substrate, the multimodal transistor device comprising: recessed metal source/drain structures formed in the substrate to be laterally spaced apart from one another; an epitaxial semiconductor channel layer formed in the substrate to cover and extend over the recessed metal source/drain structures; a channel control electrode positioned over the epitaxial semiconductor channel layer to extend between the metal source/drain structures; and a current control electrode positioned over part of the epitaxial semiconductor channel layer and over one of the metal source/drain structures to control current flow in the epitaxial semiconductor channel layer, where the current control electrode is isolated from the channel control electrode by an insulator layer.

Description

BACKGROUND OF THE INVENTION Field of the Invention The present disclosure is directed in general to the field of semiconductor devices. In one aspect, the present disclosure relates to integrated multimodal transistor devices with field effect transistor (FET) devices and methods of fabricating same. Description of the Related Art As semiconductor device sizes are scaled down, the requirements for device design and fabrication continue to be tightened in order to fit more circuitry on smaller chips. As device sizes shrink, increasingly complex process integrations are used to define semiconductor device features and structures. For example, finFET transistors replaced planar FET transistors as the leading edge transistor architecture for 1 Xnm nodes, but with next-generation technologies, stacked nanosheet transistors are in line to replace finFETs as the leading edge transistor architecture starting at the 3 nm node, followed by forksheet devices at the 2 nm node, stacked complementary nanosheet FETs, and so on. However, the existing and projected FET devices employ thin film transistor (TFT) designs having a single gate electrode in the channel region to control both charge injection and switching functions of the device, resulting in the drain current having a quadratic response to the applied gate electrode voltage. Unfortunately, the transfer characteristics for conventional TFT designs are not well suited for computational approaches increasingly required by artificial intelligence applications, such as artificial neural networks which require rectified linear unit (ReLU) activation functions having a linear dependence between the input device voltage and output (drain) current. While multimodal transistor (MMT) devices have recently been proposed as TFT devices which have a linear drain current response to the gate voltage(s), existing MMTs have been demonstrated on silicon using large dimensions and high operating voltages. Thus, existing semiconductor processes for fabricating leading edge FET transistors have not been integrated with the MMT device fabrication processes by virtue of the challenges with fabricating leading edge FET devices with additional MMT device circuit elements while meeting the performance requirements and cost constraints. Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow. BRIEF DESCRIPTION OF THE DRAWINGS The present invention may be understood, and its numerous objects, features and advantages obtained, when the following detailed description of a preferred embodiment is considered in conjunction with the following drawings. FIG. 1 is a partial cross-sectional view of a semiconductor structure having a nanosheet region and multimodal transistor (MMT) region including a semiconductor layer disposed over a buried oxide substrate in accordance with selected embodiments of the present disclosure. FIG. 2 illustrates processing subsequent to FIG. 1 after etching buried source/drain openings in the MMT region that extend through the semiconductor layer and into the buried oxide substrate in accordance with selected embodiments of the present disclosure. FIG. 3 illustrates processing subsequent to FIG. 2 after forming one or more metal source/drain layers in the etching buried source/drain openings in accordance with selected embodiments of the present disclosure. FIG. 4 illustrates processing subsequent to FIG. 3 after planarizing the one or more metal source/drain layers with the semiconductor layer in accordance with selected embodiments of the present disclosure. FIG. 5 illustrates processing subsequent to FIG. 4 after recessing the one or more metal source/drain layers below the semiconductor layer to form recessed buried metal source/drain structures in accordance with selected embodiments of the present disclosure. FIG. 6 illustrates processing subsequent to FIG. 5 after epitaxially growing and polishing a semiconductor channel layer over the recessed buried metal source/drain structures in accordance with selected embodiments of the present disclosure. FIG. 7 illustrates processing subsequent to FIG. 6 after forming a masking oxide layer over at least the MMT region in accordance with selected embodiments of the present disclosure. FIG. 8 illustrates processing subsequent to FIG. 7 after patterning and etching a Si/SiGe superlattice of alternating silicon nanosheets and silicon germanium nanosheets to form a nanosheet transistor stack over the nanosheet region in accordance with selected embodiments of the present disclosure. FIG. 9 illustrates processing subsequent to FIG. 8 after forming inner nitride spacers on sidewalls of the nanosheet transistor stack in accordance with selected embodiments of the present disclosure. FIG. 10 illustrates processing subsequent to FIG.