US-12622056-B2 - Array substrate, display panel and display device

US12622056B2US 12622056 B2US12622056 B2US 12622056B2US-12622056-B2

Abstract

Disclosed are an array substrate, a display panel, and a display device for mitigating microscopic moiré. The array substrate includes: first signal lines, and second signal lines. Each second signal line includes: first portions extending along the column direction, and second portions; the second portion includes parts extending along the included direction, and the second portion connects two first portions; an included angle between the included direction and the column direction, and an included angle between the included direction and the row direction are greater than 0; and the first portion is adjacent to an opening region of a sub-pixel unit in the row direction, the plurality of second portions each pass through a region between two adjacent pixel repeating unit rows of at least partial pixel repeating unit rows, and a distance between two first portions connected with the second portion in the row direction is greater than 0.

Inventors

Changfeng LI
Fuqiang Li
Zhongyuan Wu
Lizhen Zhang
Hongrun Wang
Jing Yu

Assignees

BEIJING SHIYAN TECHNOLOGY CO., LTD.

Dates

Publication Date: 20260505
Application Date: 20230825
Priority Date: 20221226

Claims (18)

1 . An array substrate, comprising: a base substrate; and a plurality of sub-pixel units, a plurality of first signal lines and a plurality of second signal lines on a side of the base substrate; wherein the plurality of first signal lines and the plurality of second signal lines intersect with each other to define opening regions of the plurality of sub-pixel units; the plurality of sub-pixel units are arranged in an array along a row direction and a column direction, the plurality of sub-pixel units spaced apart along the row direction form a pixel island, a plurality of pixel islands arranged consecutively along the column direction form a pixel repeating unit; and one row of pixel repeating units arranged along the row direction form a pixel repeating unit row, and opening regions of one row of sub-pixel units arranged along the row direction form an opening region row; the plurality of first signal lines are arranged along the column direction, and the plurality of second signal lines are arranged along the row direction; each of the plurality of second signal lines comprises: a plurality of first portions extending along the column direction, and a plurality of second portions; the second portion comprises parts extending along an inclined direction, and the second portion connects two of the plurality of first portions; and an included angle between the inclined direction and the column direction and an included angle between the inclined direction and the row direction are greater than 0; and the first portion is adjacent to the opening region of the sub-pixel in the row direction, the plurality of second portions respectively pass through a region between two adjacent pixel repeating unit rows of at least partial pixel repeating unit rows, and a distance between two first portions connected with the second portion in the row direction is greater than 0; wherein the plurality of first signal lines comprise: a plurality of first scanning lines and a plurality of second scanning lines; and the first scanning lines and the second scanning lines are alternately arranged; sub-pixel units in a same row are electrically connected with one of the plurality of first scanning lines and one of the plurality of second scanning lines, and the first scanning line and the second scanning line correspondingly electrically connected with the sub-pixel units in the same row are on two sides of the opening region row in the column direction; the plurality of second signal lines comprise: a plurality of data lines and a plurality of common electrode lines; and the data line and the common electrode line are alternately arranged; each of the plurality of data lines is electrically connected with two columns of sub-pixel units adjacent to the data line in the row direction; the sub-pixel unit comprises a thin film transistor; and a gate electrode of the thin film transistor is electrically connected with the first signal line and a source electrode of the thin film transistor is electrically connected with the data line; and in two adjacent rows of sub-pixel units, two thin film transistors electrically connected with a same data line share one source electrode; wherein active layers of two thin film transistors electrically connected with the second portion in the data line are integrally connected; and the second portion in the data line is electrically connected with the active layers integrally connected only through one first via hole.
2 . The array substrate according to claim 1 , wherein the second portion comprises: two first subparts extending along the inclined direction and parallel to each other, and a second subpart connecting the two first subparts; wherein the second subpart extends along the column direction, and the two first subparts are connected with different first portions, respectively.
3 . The array substrate according to claim 2 , wherein an orthographic projection of one of the two first subparts on the base substrate overlaps with an orthographic projection of the first scanning line on the base substrate, and an orthographic projection of the other of the two first subparts on the base substrate overlaps with an orthographic projection of the second scanning line on the base substrate; and an orthographic projection of the second subpart on the base substrate and an orthographic projection of the first signal line on the base substrate do not overlap with each other.
4 . The array substrate according to claim 1 , wherein each of the plurality of second signal lines further comprises: a plurality of third portions; and first portions other than the first portions connected through the second portions are connected through the plurality of third portions; two first portions connected through the third portion are on a same straight line in the column direction; the third portion comprises: a third subpart extending along a first inclined direction, a fourth subpart extending along a second inclined direction, and a fifth subpart extending along the column direction; two ends of the fifth subpart are electrically connected with the third subpart and the fourth subpart, respectively; and the third subpart and the fourth subpart are electrically connected with two different first portions, respectively; the first inclined direction intersects with the second inclined direction; and two first portions connected through the third portion are on a same straight line in the column direction.
5 . The array substrate according to claim 4 , wherein an orthographic projection of the third subpart on the base substrate overlaps with an orthographic projection of the second scanning line on the base substrate, and an orthographic projection of the fourth subpart on the base substrate overlaps with an orthographic projection of the first scanning line on the base substrate; and an orthographic projection of the fifth subpart on the base substrate and an orthographic projection of the first signal line on the base substrate do not overlap with each other.
6 . The array substrate according to claim 4 , wherein active layers of two thin film transistors electrically connected with the third portion are integrally connected, and the third portion is electrically connected with the active layers electrically connected integrally only through one first via hole.
7 . The array substrate according to claim 4 , wherein the opening regions of the sub-pixels in any two adjacent pixel repeating unit rows are misaligned in the row direction; an orthographic projection of the second portion on the base substrate overlaps with an orthographic projection of a region between two adjacent opening region rows which are respectively located in two different pixel repeating unit rows on the base substrate; and an orthographic projection of the third portion on the base substrate overlaps with an orthographic projection of a region between two adjacent opening region rows in the same pixel repeating unit row on the base substrate.
8 . The array substrate according to claim 7 , wherein in the row direction, a ratio of a width of the opening region of the sub-pixel unit to a width of the pixel island is i/M, wherein M is an integer greater than 1, and i is an integer greater than or equal to 1 and less than M; the plurality of pixel repeating unit rows are divided into a plurality of pixel repeating unit groups, and each of the plurality of pixel repeating unit groups comprises M pixel repeating unit rows; and in each of the plurality of pixel repeating unit groups, a ratio of a misalignment vector of a first portion corresponding to a j th pixel repeating unit row with respect to a first portion corresponding to a 1 st pixel repeating unit row in the row direction to the width of the opening region of the sub-pixel unit in the row direction is Jj=±E/M, wherein j is an integer greater than 1 and less than or equal to M, and E is an integer greater than or equal to 1 and less than M.
9 . The array substrate according to claim 4 , wherein the sub-pixel unit further comprises a pixel electrode electrically connected with the thin film transistor; an orthographic projection of the pixel electrode on the base substrate is non-rectangular; and an edge of the pixel electrode adjacent to the second signal line has a shape of a folded line; the pixel electrode is divided into a sixth portion adjacent to the first portion, and a seventh portion connected with the sixth portion and adjacent to the second portion or the third portion; and an edge of the seventh portion adjacent to the second signal line extends along the column direction, and an included angle between at least part of an edge of the sixth portion adjacent to the second signal line and the column direction is greater than 0.
10 . The array substrate according to claim 9 , further comprising a common electrode electrically connected with the common electrode line; wherein the common electrode is on a side of the pixel electrode facing away from the base substrate; the common electrode comprises: a first pattern layer, and a second pattern layer on a side of the first pattern layer facing away from the base substrate; wherein the first pattern layer is electrically connected with the second pattern layer; the first pattern layer comprises a plurality of first striped portions arranged along the row direction and extending along the column direction, and first opening regions between the plurality of first striped portions; the second pattern layer comprises a plurality of second striped portions arranged along the row direction and extending along the column direction; wherein a distance between the first striped portion and the second striped portion is greater than 0 in the row direction; and an orthographic projection of the first striped portion on the base substrate covers an orthographic projection of the second signal line on the base substrate, the orthographic projection of the first striped portion on the base substrate and an orthographic projection of the pixel electrode on the base substrate do not overlap with each other, and an orthographic projection of the second striped portion on the base substrate overlaps with an orthographic projection of the pixel electrode on the base substrate.
11 . The array substrate according to claim 10 , wherein in the row direction, a distance between the pixel electrode and the first striped portion is greater than 0.
12 . The array substrate according to claim 10 , wherein the first striped portion comprises: a first sub-layer and a second sub-layer stacked in a direction perpendicular to the base substrate; the second sub-layer is on a side of the first sub-layer facing away from the base substrate; in the row direction, a width of the first sub-layer is greater than a width of the second sub-layer; and an orthographic projection of the second sub-layer on the base substrate is within an orthographic projection of the first sub-layer on the base substrate.
13 . The array substrate according to claim 10 , wherein the first pattern layer further comprises a third striped portion extending along the row direction and connected with the plurality of first striped portions, and the second pattern layer further comprises a fourth striped portion extending along the row direction and connected with the plurality of second striped portions; and an orthographic projection of the fourth striped portion on the base substrate overlaps with an orthographic projection of the third striped portion on the base substrate, and the second pattern layer covers an edge of the third striped portion close to a side of the first opening region.
14 . The array substrate according to claim 13 , wherein in the column direction, orthographic projections of two third striped portions on both sides of the first opening region on the base substrate overlap with an orthographic projection of the pixel electrode on the base substrate.
15 . The array substrate according to claim 10 , wherein an orthographic projection of the common electrode on the base substrate and an orthographic projection of the gate electrode of the thin film transistor on the base substrate do not overlap with each other.
16 . A display panel, comprising: the array substrate according to claim 1 ; an opposite substrate opposite to the array substrate; and a liquid crystal layer between the array substrate and the opposite substrate.
17 . A display device, comprising the display panel according to claim 16 .
18 . The display device according to claim 17 , comprising: a light splitting assembly on a display side of the display panel; wherein the light splitting assembly comprises a plurality of light splitting repeating units extending along the column direction and continuously arranged along the row direction; the light splitting repeating unit comprises M light splitting structures extending along the column direction and continuously arranged along the row direction; and each of the plurality of light splitting repeating units corresponds to N columns of sub-pixel units in the pixel repeating unit row; wherein M and N are both integers greater than 1, and M and N are relatively prime.

Description

CROSS REFERENCE TO RELATED APPLICATIONS The present disclosure is a National Stage of International Application No. PCT/CN2023/115080, filed Aug. 25, 2023, which claims priority to the Chinese patent application No. 202211679554. X, filed on Dec. 26, 2022 to the China National Intellectual Property Administration, and entitled “Array Substrate, Display Panel and Display Device”, the entire content of which is incorporated herein by reference. TECHNICAL FIELD The present disclosure relates to the technical field of display, in particular to an array substrate, a display panel and a display device. BACKGROUND With the continuous development of the display technology, the three-dimensional (3D) display technology is getting more and more attention. Three-dimensional display technology can make the display screen become stereoscopic and realistic. The principle is that: by using the left and right eyes of a person to respectively receive a left eye image and a right eye image with a certain parallax, after the two parallax images are received by the left and right eyes of a person respectively, the brain superimposes and fuses the image information, and a 3D visual display effect is built. In order to realize the compatibility of the ultra-multiple viewpoint 3D display and the light field display, a conventional sub-pixel is made into a pixel island structure, and each pixel island includes a plurality of sub-pixels, so that when the display information of the plurality of sub-pixels is different and a single eye enters into a plurality of viewpoints, the ordinary light field display can be realized, and when the display information of the plurality of sub-pixels is different and a single eye enters into a single viewpoint, the ultra-multiple viewpoint light field 3D display can be realized. However, the 3D display products in the prior art have the problem of moiré. SUMMARY Embodiments of the present disclosure provide an array substrate, a display panel and a display device, for mitigating microscopic moiré. Embodiments of the present disclosure provide an array substrate, including: a base substrate; and a plurality of sub-pixel units, a plurality of first signal lines and a plurality of second signal lines on a side of the base substrate. The plurality of first signal lines and the plurality of second signal lines intersect with each other to define opening regions of the plurality of sub-pixel units; the plurality of sub-pixel units are arranged in an array along a row direction and a column direction, the plurality of sub-pixel units spaced apart along the row direction form a pixel island, a plurality of pixel islands arranged consecutively along the column direction form a pixel repeating unit; and one row of pixel repeating units arranged along the row direction form a pixel repeating unit row, and opening regions of one row of sub-pixel units arranged along the row direction form an opening region row; the plurality of first signal lines are arranged along the column direction, and the plurality of second signal lines are arranged along the row direction; each of the plurality of second signal lines includes: a plurality of first portions extending along the column direction, and a plurality of second portions; the second portion includes parts extending along an inclined direction, and the second portion connects two of the plurality of first portions; and an included angle between the inclined direction and the column direction and an included angle between the inclined direction and the row direction are greater than 0; and the first portion is adjacent to the opening region of the sub-pixel in the row direction, the plurality of second portions each pass through a region between two adjacent pixel repeating unit rows of at least partial pixel repeating unit rows, and a distance between two first portions connected with the second portion in the row direction is greater than 0. In some embodiments, the plurality of first signal lines include: a plurality of first scanning lines and a plurality of second scanning lines; and the plurality of first scanning lines and the plurality of second scanning lines are sequentially alternated; sub-pixel units in a same row are electrically connected with one of the plurality of first scanning lines and one of the plurality of second scanning lines, and the first scanning line and the second scanning line correspondingly electrically connected with the sub-pixel units in the same row of are on two sides of the opening region row in the column direction; the plurality of second signal lines include: a plurality of data lines and a plurality of common electrode lines; and the plurality of data lines and the plurality of common electrode lines are alternately arranged; each of the plurality of data lines is electrically connected with two columns of sub-pixel units adjacent to the data line in the row direction; the sub-pixel unit includes a thin film transistor; a