US-12622064-B2 - Integrated standard cell structure

US12622064B2US 12622064 B2US12622064 B2US 12622064B2US-12622064-B2

Abstract

An integrated circuit (IC) structure includes a fin structure protruding from a semiconductor substrate, the fin structure including a first portion having a first width, a second portion having a second width that is different from the first width, and a third portion extending continuously along a first direction over the semiconductor substrate, the first width and the second width being measured along a second direction perpendicular to the first direction. The IC structure also includes a first standard cell including a first metal gate stack engaged with the first portion, a second standard cell including a second metal gate stack engaged with the second portion, and a filler cell disposed between the first standard cell and the second standard cell, where the filler cell includes the third portion that connects the first portion to the second portion. The IC further includes a dielectric gate defining a first boundary of the filler cell and a third metal gate stack defining a second boundary of the filler cell, where the dielectric gate and the third metal gate stack are separated by a one-pitch spacing.

Inventors

Shih-Hsien Huang
Cheng-Hua Liu
Kuang-Hung CHANG
Sheng-Hsiung Wang
Chun-Yen Lin
Tung-Heng Hsieh
Bao-Ru Young

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date: 20260505
Application Date: 20220610

Claims (20)

1 . An integrated circuit structure, comprising: a semiconductor substrate; a fin structure protruding from the semiconductor substrate, including a first portion having a first width, a second portion having a second width that is different from the first width, and a third portion extending continuously along a first direction over the semiconductor substrate, the first width and the second width being measured along a second direction perpendicular to the first direction; a first standard cell including a first metal gate stack engaged with the first portion; a second standard cell including a second metal gate stack engaged with the second portion; a filler cell disposed between the first standard cell and the second standard cell, wherein the filler cell includes the third portion that connects the first portion to the second portion; a dielectric gate different in composition from the first and second metal gate stacks and defining a first boundary of the filler cell; and a third metal gate stack defining a second boundary of the filler cell, wherein the dielectric gate and the third metal gate stack are separated by a one-pitch spacing P.
2 . The integrated circuit structure of claim 1 , wherein the dielectric gate defines a boundary of the first standard cell and the third metal gate stack defines a boundary of the second standard cell.
3 . The integrated circuit structure of claim 1 , wherein the first metal gate stack and the second metal gate stack are configured as functional metal gate stacks and the third metal gate stack is configured as a dummy metal gate stack.
4 . The integrated circuit structure of claim 1 , wherein the third portion has a sidewall horizontally aligned with a sidewall of the first portion or the third second portion, and the sidewall of the third portion spans a distance between the dielectric gate and the third metal gate stack.
5 . The integrated circuit structure of claim 1 , wherein the filler cell abuts the first standard cell and the second standard cell.
6 . The integrated circuit structure of claim 1 , wherein the first standard cell and the second standard cell each span a lateral distance of no more than 3*P.
7 . An integrated circuit structure, comprising: a fin structure including a first portion having a first width, a second portion having a second width, and a third portion having a third width, the fin structure protruding from a semiconductor substrate and extending lengthwise along a first direction, wherein the third portion extends from the first portion to the second portion, wherein the second width differs from the first width, and wherein sidewalls of the second and the third portions form an L-shaped step profile defined by an exposed surface of the second portion extending from a sidewall of the second portion to a sidewall of the third portion along a second direction different from the first direction; a first transistor in a first standard cell, wherein the first transistor includes a first metal gate stack engaged with the first portion; a second transistor in a second standard cell, wherein the second transistor includes a second metal gate stack engaged with the second portion; a dielectric gate different in composition from the first and second metal gate stacks and disposed between the first metal gate stack and the second metal gate stack; a third metal gate stack disposed between the dielectric gate and the second metal gate stack, wherein the third metal gate stack is inactive; and a filler cell sandwiched between the first standard cell and the second standard cell, wherein boundaries of the filler cell are defined by the dielectric gate and the third metal gate stack, and wherein the third portion extends across a width of the filler cell.
8 . The integrated circuit structure of claim 7 , wherein the filler cell is free of any transistor.
9 . The integrated circuit structure of claim 7 , wherein the first standard cell and the second standard cell include the same number of transistors.
10 . The integrated circuit structure of claim 7 , wherein the second width is less than the first width.
11 . The integrated circuit structure of claim 7 , wherein the second width is greater than the third width.
12 . The integrated circuit structure of claim 7 , wherein the first standard cell further includes a third transistor, wherein the third transistor includes the first metal gate stack engaged with a fourth portion of the fin structure, the fourth portion having a fourth width that is greater than the first width.
13 . The integrated circuit structure of claim 12 , wherein the first transistor is of n-type and the third transistor is of p-type.
14 . The integrated circuit structure of claim 12 , wherein a width of the filler cell is one gate pitch P.
15 . The integrated circuit structure of claim 12 , wherein the second metal gate stack and the third metal gate stack are separated by one gate pitch P.
16 . The integrated circuit structure of claim 12 , wherein the third metal gate stack is configured with the same structure as the first metal gate stack or the second metal gate stack.
17 . The integrated circuit structure of claim 12 , wherein the filler cell is a first filler cell, the integrated circuit further comprising: a fourth metal gate stack disposed between the first metal gate stack and the dielectric gate; and a second filler cell with boundaries defined by the fourth metal gate stack and the dielectric gate.
18 . The integrated circuit structure of claim 17 , wherein the fourth metal gate stack and the dielectric gate are separated by one gate pitch P.
19 . An integrated circuit structure, comprising: a fin structure including a first portion, a second portion, and a third portion over a substrate, wherein the third portion extends continuously in a first direction between the first portion and the second portion, and wherein the second portion and the third portion differ in a width measured along a second direction perpendicular to the first direction, wherein the first, the second, and the third portions of the fin structure are horizontally aligned on a first side of the fin structure along the first direction and horizontally misaligned on a second side of the fin structure along the first direction; and a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure each oriented lengthwise in the second direction, wherein the first gate structure and the second gate structure engage with the first portion and the second portion, respectively, and wherein the third gate structure and the fourth gate structure are disposed between the first gate structure and the second gate structure, wherein the third gate structure is a dielectric gate different in composition from the first and second gate structures, wherein the first gate structure, the second gate structure, and the fourth gate structure are metal gates, thereby forming first, second, and third metal gates, respectively, wherein: the first metal gate engages with the first portion to form a first transistor in a first standard (STD) cell, the second metal gate engages with the second portion to form a first transistor in a second STD cell, the third metal gate defines a first boundary of a filler cell sandwiched between the first STD cell and the second STD cell, the dielectric gate defines a second boundary of the filler cell, and the third portion spans a width of the filler cell.
20 . The integrated circuit structure of claim 19 , wherein the first portion, the second portion, and the third portion are formed in a first doped region of the substrate, the fin structure further comprising a fourth portion, a fifth portion, and a sixth portion disposed in a second doped region adjacent the first doped region along the second direction, the first doped region and the second doped region having dopants of different conductivity types, wherein: the first metal gate and the second metal gate is engaged with the fourth portion and the fifth portion to form a second transistor in the first STD cell and a second transistor in the second STD cell, respectively.

Description

BACKGROUND In the design of integrated circuits (IC), standard (STD) cells with certain functions are repeated used with high frequency. Accordingly, those standard cells are predesigned and packed in a cell library. The cell library is provided to the IC designers for their particular designing. During integrated circuit designing, the standard cells are retrieved from the cell libraries and placed into desired locations, thus reducing the design effort. Routing is then performed to connect the standard cells and other circuit blocks to form the desired integrated circuit. Pre-defined design rules are followed when placing the standard cells into the desired locations. During IC manufacturing, it may be desirable to integrate STD cells of various sizes and/or structures to provide design flexibility and to achieve specific target performance at reduced length scales. One such example may be the variation in fin widths across different STD cells. While methods of forming such layout are generally adequate, they have not been entirely satisfactory in all aspects. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIGS. 1, 3, 5, and 7 are top views of an example semiconductor structure, or a portion thereof, according to various aspects of the present disclosure. FIGS. 2A, 4A, and 6A are cross-sectional views of the example semiconductor structure taken along line AA′ of FIGS. 1, 3, and 5, respectively, according to various aspects of the present disclosure. FIGS. 2B, 4B, and 6B are cross-sectional views of the example semiconductor structure taken along line BB′ of FIGS. 1, 3, and 5, respectively, according to various aspects of the present disclosure. FIGS. 2C, 4C, and 6C are cross-sectional views of the example semiconductor structure taken along line CC′ of FIGS. 1, 3, and 5, respectively, according to various aspects of the present disclosure. FIG. 6D is a cross-sectional view of the example semiconductor structure depicted in FIG. 5 along line DD′, according to various aspects of the present disclosure. FIG. 8 is a flowchart of an example method of fabricating a semiconductor structure, according to various aspects of the present disclosure. FIG. 9 is a flowchart of an example method of fabricating a semiconductor structure, according to various aspects of the present disclosure. FIGS. 10, 12, 14, 16, 18A, 20, 22, 24, 26, 28, and 30 are top views of an example semiconductor structure at intermediate steps of the methods depicted in FIGS. 8 and/or 9, according to various aspects of the present disclosure. FIGS. 11A, 13A-13C, 15A-15C, 17A-17C, 19A-19C, 21A-21C, 23A-23C, 25A-25C, 27A-27C, 29A-29C, and 31A-31C are cross-sectional views of the example semiconductor structure taken along line AA′ of FIGS. 10, 12, 14, 16, 18A, 20, 22, 24, 26, 28, and 30, respectively, at intermediate steps of the methods depicted in FIGS. 8 and/or 9, according to various aspects of the present disclosure. FIGS. 11B, 13D-13F, 15D-15F, 17D-17F, 19D-19F, 21D-21F, 23D-23F, 25D-25F, 27D-27F, 29D-29F, and 31D-31F are cross-sectional views of the example semiconductor structure taken along line BB′ of FIGS. 10, 12, 14, 16, 18A, 20, 22, 24, 26, 28, and 30, respectively, at intermediate steps of the methods depicted in FIGS. 8 and/or 9, according to various aspects of the present disclosure. FIGS. 18B, 18C, 18D, and 18E are top views of various embodiments of an example semiconductor structure at intermediate steps of the methods depicted in FIGS. 8 and/or 9. DETAILED DESCRIPTION It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of various embodiments. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for