US-12622065-B2 - Electrostatic discharge protection device

Abstract

An electrostatic discharge protection device is provided. The electrostatic discharge protection device includes first and second N-type deep well (DNW) regions in a P-type semiconductor substrate, first to fourth N-type and P-type doped regions, and first and second P-type well (PW) regions. The first N-type and P-type doped regions and the first PW region are located in the first DNW region. The second N-type and P-type doped regions and the second PW region are located in the second DNW region. The third and fourth N-type and P-type doped regions are located in the first and second PW regions. The first P-type and fourth N-type doped regions are connected to an input/output terminal. The first N-type and second P-type doped regions are connected to a power supply terminal. The third N-type and the fourth P-type doped regions are connected to a ground terminal.

Inventors

• Ke-Yuan Chen

Assignees

• VIA TECHNOLOGIES, INC.

Dates

Publication Date

20260505

Application Date

20230406

Priority Date

20230104

Claims (18)

1. 1 . An electrostatic discharge protection device, comprising: a P-type semiconductor substrate; a first N-type deep well region located in the P-type semiconductor substrate; a first N-type doped region located in the first N-type deep well region; first P-type doped regions located in the first N-type deep well region, wherein the first P-type doped regions and the first N-type doped region are arranged side-by-side and spaced apart from each other; a second N-type deep well region located in the P-type semiconductor substrate, wherein the second N-type deep well region and the first N-type deep well region are arranged side-by-side and spaced apart from each other; second N-type doped regions located in the second N-type deep well region; second P-type doped regions located in the second N-type deep well region, wherein the second P-type doped regions and the second N-type doped regions are arranged side-by-side and spaced apart from each other; a first P-type well region located in the first N-type deep well region; third N-type doped regions located in the first P-type well region; third P-type doped regions located in the first P-type well region, wherein the third P-type doped regions and the third N-type doped regions are arranged side-by-side and spaced apart from each other; a second P-type well region located in the second N-type deep well region; fourth N-type doped regions located in the second P-type well region; and a fourth P-type doped region located in the second P-type well region, wherein the fourth P-type doped region and the fourth N-type doped regions are arranged side-by-side and spaced apart from each other; wherein the first P-type well region, the first N-type doped region and the first P-type doped regions disposed in the first N-type deep well region, and the third N-type doped regions and the third P-type doped regions disposed in the first P-type well region are arranged symmetrically along an axis passing through a center of the first N-type doped region along an extending direction of the first N-type doped region, wherein the first P-type doped regions and the fourth N-type doped regions are electrically connected to an input/output terminal, wherein the first N-type doped region and the second P-type doped regions are electrically connected to a power supply terminal, and wherein the third N-type doped regions and the fourth P-type doped region are electrically connected to a ground terminal.
2. 2 . The electrostatic discharge protection device as claimed in claim 1 , further comprising: a first guard ring located in the P-type semiconductor substrate and surrounding the first N-type deep well region and the second N-type deep well region, wherein the first guard ring comprises: a third P-well region; and a fifth P-type doped region located in the third P-type well region; and a second guard ring located in the P-type semiconductor substrate and surrounding the first guard ring, wherein the second guard ring comprises: a first N-type well region; and a fifth N-type doped region located in the first N-type well region.
3. 3 . The electrostatic discharge protection device as claimed in claim 2 , wherein the fifth P-type doped region is electrically connected to the ground terminal.
4. 4 . The electrostatic discharge protection device as claimed in claim 2 , wherein the fifth N-type doped region is electrically connected to the power supply terminal.
5. 5 . The electrostatic discharge protection device as claimed in claim 1 , wherein the third P-type doped regions and the second N-type doped regions are electrically connected to a switching circuit.
6. 6 . The electrostatic discharge protection device as claimed in claim 5 , wherein when an electrostatic discharge event occurs at the input/output terminal, the power supply terminal or the ground terminal, the third P-type doped regions are electrically connected to the power supply terminal, and the second N-type doped region is electrically connected to the ground terminal.
7. 7 . The electrostatic discharge protection device as claimed in claim 6 , wherein each of the first P-type doped regions, the first N-type deep well region and the first N-type doped region form a first parasitic diode, and wherein the fourth P-type doped region, the second P-type well region and each of the fourth N-type doped regions form a second parasitic diode.
8. 8 . The electrostatic discharge protection device as claimed in claim 7 , wherein when an electrostatic discharge event occurs between the input/output terminal and the power supply terminal, the first parasitic diode is triggered to ON.
9. 9 . The electrostatic discharge protection device as claimed in claim 7 , wherein when an electrostatic discharge event occurs between the ground terminal and the input/output terminal, the second parasitic diode is triggered to ON.
10. 10 . The electrostatic discharge protection device as claimed in claim 7 , wherein: each of the first P-type doped regions, the first N-type deep well region and the first P-type well region form a first parasitic bipolar junction transistor, each of the third N-type doped regions, the first P-type well region and the first N-type deep well region form a second parasitic bipolar junction transistor, a base of the first parasitic bipolar junction transistor is electrically connected to a collector of the second parasitic bipolar junction transistor, and a base of the second parasitic bipolar junction transistor is electrically connected to a collector of the first parasitic bipolar junction transistor to form a first parasitic semiconductor controlled rectifier, an emitter of the first parasitic bipolar junction transistor is electrically connected to the input/output terminal and an anode of the first parasitic diode, the base of the first parasitic bipolar junction transistor is electrically connected to a cathode of the first parasitic diode, and an emitter of the second parasitic bipolar junction transistor is electrically connected to the ground terminal.
11. 11 . The electrostatic discharge protection device as claimed in claim 7 , wherein: each of the second P-type doped regions and the second N-type deep well region form a third parasitic diode, each of the second P-type doped regions, the second N-type deep well region and the second P-type well region form a third parasitic bipolar junction transistor, each of the fourth N-type doped regions, the second P-type well region and the second N-type deep well region form a fourth parasitic bipolar junction transistor, a base of the third parasitic bipolar junction transistor is electrically connected to a collector of the fourth parasitic bipolar junction transistor, and a base of the fourth parasitic bipolar junction transistor is electrically connected to a collector of the third parasitic bipolar junction transistor to form a second parasitic semiconductor controlled rectifier, an emitter of the third parasitic bipolar junction transistor is electrically connected to the power supply terminal and an anode of the third parasitic diode, the base of the third parasitic bipolar junction transistor is electrically connected to a cathode of the third parasitic diode, an emitter of the fourth parasitic bipolar junction transistor is electrically connected to the input/output terminal and a cathode of the second parasitic diode, and the base of the fourth parasitic bipolar junction transistor is electrically connected to an anode of the second parasitic diode.
12. 12 . The electrostatic discharge protection device as claimed in claim 1 , further comprising: a first gate structure disposed on the first N-type deep well region in the P-type semiconductor substrate, partially overlapping one of the first P-type doped regions and a sixth P-type doped region disposed in the first N-type deep well region, wherein the sixth P-type doped region is electrically connected to the power supply terminal, wherein the first gate structure, the one of the first P-type doped regions and the sixth P-type doped region form a first P-type metal-oxide-semiconductor transistor.
13. 13 . The electrostatic discharge protection device as claimed in claim 1 , further comprising: a second gate structure disposed on the second P-type well region in the P-type semiconductor substrate, partially overlapping one of the fourth N-type doped regions and a sixth N-type doped region disposed in the second P-type deep well region, wherein the sixth N-type doped region is electrically connected to the ground terminal, wherein the second gate structure, the one of the fourth N-type doped regions and the sixth N-type doped region form a first N-type metal-oxide-semiconductor transistor.
14. 14 . The electrostatic discharge protection device as claimed in claim 1 , further comprising: a third gate structure disposed on the first P-type well region in the P-type semiconductor substrate, partially overlapping one of the third P-type doped regions and a seventh N-type doped region disposed in the first P-type well region, wherein the third gate structure is electrically connected to the power supply terminal, and the seventh N-type doped region is electrically connected to the ground terminal, wherein the third gate structure, the one of the third P-type doped regions and the seventh N-type doped region form a first capacitor.
15. 15 . The electrostatic discharge protection device as claimed in claim 1 , further comprising: a fourth gate structure disposed on the second N-type deep well region in the P-type semiconductor substrate, partially overlapping one of the second N-type doped regions and a seventh P-type doped region disposed in the second N-type deep well region, wherein the fourth gate structure is electrically connected to the ground terminal, and the seventh P-type doped region is electrically connected to the power supply terminal, wherein the fourth gate structure, the one of the second N-type doped regions and the seventh P-type doped region form a second capacitor.
16. 16 . The electrostatic discharge protection device as claimed in claim 1 , further comprising: a conductive line disposed over the P-type semiconductor substrate, wherein two ends of the conductive line are directly and electrically connected to one of the third P-type doped regions and one of the second N-type doped regions, respectively.
17. 17 . The electrostatic discharge protection device as claimed in claim 1 , further comprising: a fourth diode disposed over the P-type semiconductor substrate, wherein an anode and a cathode of the fourth diode are electrically connected to one of the second N-type doped regions and one of the third P-type doped regions, respectively.
18. 18 . The electrostatic discharge protection device as claimed in claim 1 , further comprising: a second N-type metal-oxide-semiconductor transistor having a base, a gate, a first source/drain and a second source/drain; and a detection circuit, wherein the base is electrically connected to the ground terminal, wherein the gate is electrically connected to the detection circuit, the first source/drain is electrically connected to one of the third P-type doped regions, and the second source/drain is electrically connected to one of the second N-type doped regions.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This application claims priority of Taiwan Patent Application No. 112100211, filed on Jan. 4, 2023, the entirety of which is incorporated by reference herein. BACKGROUND OF THE INVENTION Field of the Invention The present disclosure relates to an electrostatic discharge protection device, and, in particular, to the structure and layout of the electrostatic discharge protection device. Description of the Related Art Integrated circuits (ICs) include semiconductor devices that are susceptible to damage from electrical overstress conditions (EOS) which includes electrostatic discharge (ESD), transient conditions, latch-up, and incorrect polarity connections. The electrical overstress conditions are characterized by over-voltage and over-current stress events. Electrostatic charge (ESC) would accumulate in IC package, manufacturing machine or operator and it would damage semiconductor devices and circuitry therein if the IC is stressed by the charge. This phenomenon is called electrostatic discharge. Therefore, how to protect semiconductor devices from ESD or other electrical overvoltage conditions is a problem that needs to be solved. In addition, for high-speed and high-end chips, a conventional ESD protection circuit using diodes or transistors cannot solve the ESD problem. BRIEF SUMMARY OF THE INVENTION An embodiment of the disclosure provides an electrostatic discharge protection device. The electrostatic discharge protection device includes a P-type semiconductor substrate, a first N-type deep well region, a second N-type deep well region, a first N-type doped region, a first P-type doped region, a second N-type doped region, a second P-type doped region, a third N-type doped region, a third P-type doped region, a fourth N-type doped region, a fourth P-type doped region, a first P-type well region and a second P-type well region. The first N-type deep well region is located in the P-type semiconductor substrate. The first N-type doped region is located in the first N-type deep well region. The first P-type doped region is located in the first N-type deep well region. The first P-type doped region and the first N-type deep well region are arranged side-by-side and spaced from each other. The second N-type deep well region is located in the P-type semiconductor substrate. The second N-type deep well region and the first N-type deep well region are arranged side-by-side and spaced from each other. The second N-type doped region is located in the second N-type deep well region. The second P-type doped region is located in the second N-type deep well region. The second P-type doped region and the second N-type doped region are arranged side-by-side and spaced from each other. The first P-type well region is located in the first N-type deep well region. The third N-type doped region is located in the first P-type well region. The third P-type doped region is located in the first P-type well region. The third P-type doped region and the third N-type doped region are arranged side-by-side and spaced from each other. The second P-type well region is located in the second N-type deep well region. The fourth N-type doped region is located in the second P-type well region. In addition, the fourth P-type doped region is located in the second P-type well region. The fourth P-type doped region and the fourth N-type doped region are arranged side-by-side and spaced from each other. The first P-type doped region and the fourth N-type doped region are electrically connected to an input/output terminal. The first N-type doped region and the second P-type doped region are electrically connected to a power supply terminal. The third N-type doped region and the fourth P-type doped region are electrically connected to a ground terminal. BRIEF DESCRIPTION OF THE DRAWINGS The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: FIG. 1 is a schematic top view of an electrostatic discharge protection device in accordance with some embodiments of the disclosure; FIG. 2 is a schematic cross-sectional view along the line A-A′ of the electrostatic discharge protection device of FIG. 1 in accordance with some embodiments of the disclosure; FIG. 3 is a partial enlarged view of FIG. 2 showing an equivalent discharge circuit diagram of the electrostatic discharge protection device when an electrostatic discharge event occurs between the input/output terminal (IO) and the power supply terminal (VCC) or between a ground terminal (VSS) and the input/output terminal (IO), and schematic showing the parasitic elements of the equivalent discharge circuit at the corresponding positions of the electrostatic discharge protection device of FIG. 2; FIG. 4A is an equivalent discharge circuit diagram of the electrostatic discharge protection device when an electrostatic discharge event occurs between t