US-12622066-B2 - Resonance cancellation devices and methods

Abstract

Ground impedance may have adverse effects on the performance of RF circuits that employ shunt switches. The disclosed methods and devices address this issue. The methods and devices involve the use of resonance-canceling inductors to counteract the capacitive reactance caused by parasitic capacitances and/or decoupling capacitors utilized in such systems. Solutions that incorporate series resistors to distribute the resonance across the frequency band of operation are also described. Additionally, devices that employ digitally tuned capacitors to shift the resonance frequency outside the operational band are presented.

Inventors

• Joseph Porter Slaton
• Parvez DARUWALLA

Assignees

• PSEMI CORPORATION

Dates

Publication Date

20260505

Application Date

20230628

Claims (20)

1. 1 . A circuital arrangement comprising an integrated circuit (IC), the IC comprising: a shunt switch; a decoupling capacitance connecting a source terminal of the switch to a first pin of the IC; a storage capacitance disposed outside the IC and coupled to the first pin of the IC; a resonance-canceling inductance disposed outside the IC and in series with the storage capacitance; wherein: the storage capacitance acts as an alternating current (AC)-short circuit across an operational frequency band of the IC; the resonance-canceling inductance is configured to cancel or attenuate a parasitic resonance, by a combination of i) a series arrangement of a parasitic ground inductance inside the IC and a parasitic ground inductance outside the IC with ii) a parallel arrangement of the decoupling capacitance and a parasitic capacitance, the parasitic resonance to be canceled or reduced occurring at a frequency within an operational frequency band of the circuital arrangement.
2. 2 . The circuital arrangement of claim 1 , further comprising a resistor, the resistor being disposed inside the IC, in series with the decoupling capacitance and connected to the first pin of the IC.
3. 3 . The circuital arrangement of claim 2 , wherein the resistor includes an adjustable resistor.
4. 4 . The circuital arrangement of claim 1 , wherein the resonance-canceling inductance is disposed upstream of the storage capacitance.
5. 5 . The circuital arrangement of claim 1 , wherein the resonance-canceling inductance is disposed downstream of the storage capacitance.
6. 6 . The circuital arrangement of claim 1 , further comprising a first electrostatic discharge (ESD) device, the first ESD device being disposed outside the IC and connected to the first pin of the IC.
7. 7 . The circuital arrangement of claim 6 , wherein the IC further comprises a second pin, and wherein input/output (I/O) devices outside the IC are connected to the second pin.
8. 8 . The circuital arrangement of claim 7 , further comprising a second ESD device being disposed outside the IC and connected to the second pin.
9. 9 . The circuital arrangement of claim 7 , wherein the parasitic capacitance includes a parasitic capacitance of the first ESD device.
10. 10 . The circuital arrangement of claim 1 , wherein the IC is disposed on a printed circuit board (PCB), and wherein the parasitic ground inductance outside the IC is a PCB ground impedance.
11. 11 . The circuital arrangement of claim 1 , wherein the resonance-canceling inductance includes a digitally tunable inductor.
12. 12 . The circuital arrangement of claim 1 , wherein the decoupling capacitance includes a digitally tunable capacitor.
13. 13 . A circuital arrangement comprising an integrated circuit (IC), the IC comprising: a shunt switch; a decoupling capacitance connecting a source terminal of the switch to a first pin of the IC; a storage capacitance disposed outside the IC and coupled to the first pin; a resonance-canceling inductance disposed inside the IC and in series with the decoupling capacitance; wherein: the storage capacitance acts as an alternating current (AC)-short circuit across an operational frequency band of the IC; the resonance-canceling inductance is configured to cancel or attenuate a parasitic resonance, by a combination of i) a series arrangement of a parasitic ground inductance inside the IC and a parasitic ground inductance outside the IC with ii) a parallel arrangement of the decoupling capacitance and a parasitic capacitance, the parasitic resonance to be canceled or reduced occurring at a frequency within an operational frequency band of the circuital arrangement.
14. 14 . The circuital arrangement of claim 13 , further comprising a resistor, the resistor being disposed inside the IC, in series with the decoupling capacitance and the resonance-canceling inductance, the resistor being connected to the first pin of the IC.
15. 15 . The circuital arrangement of claim 13 , further comprising a first electrostatic discharge (ESD) device, the first ESD device being disposed outside the IC and connected to the first pin of the IC.
16. 16 . The circuital arrangement of claim 13 , wherein the IC is disposed on a printed circuit board (PCB), and wherein the parasitic ground inductance outside the IC is a PCB ground impedance.
17. 17 . The circuital arrangement of claim 13 , wherein the resonance-canceling inductance includes a digitally tunable inductor.
18. 18 . The circuital arrangement of claim 17 , further including a resistor disposed in series with the decoupling capacitance.
19. 19 . A circuital arrangement comprising an integrated circuit (IC), the IC comprising: a shunt switch; a decoupling capacitance connecting a source terminal of the switch to a first pin of the IC; a storage capacitance disposed outside the IC and coupled to the first pin of the IC; a resistor disposed inside the IC and in series with the storage capacitance; wherein: the storage capacitance acts as an alternating current (AC)-short circuit across an operational frequency band of the IC; the resistor is configured to attenuate a parasitic resonance, by a combination of i) a series arrangement of a parasitic ground inductance inside the IC and a parasitic ground inductance outside the IC with ii) a parallel arrangement of the decoupling capacitance and a parasitic capacitance, by spreading the parasitic resonance across an operational frequency band of the circuital arrangement.
20. 20 . The circuital arrangement of claim 19 , wherein the resistor is an adjustable resistor.

Description

TECHNICAL FIELD The present disclosure is related to resonance cancellation. More in particular, the disclosed methods and devices can be implemented in electronic circuits where storage and decoupling capacitors on input/output (I/O) pins resonate with the radio frequency (RF) ground. BACKGROUND RF switches have been used by RF engineers to implement a wide range of functions within RF circuits. For example, RF switches may be used in cellular phones to switch between different cellular bands. RF switches may also be used to selectively connection an antenna to a transmitter or a receiver. RF switches may be designed to provide isolation between signal paths, ensuring minimal interference and preserving signal quality. This capability is useful for minimizing cross-talk or spurious signals. SUMMARY The disclosed methods and devices address the above-mentioned performance degradation issues. According to the disclosed teachings, an inductor may be disposed on the IC or the PCB, the inductor being connected to the I/O pins in series with the decoupling capacitor. The inductance introduced by the added inductor will generate an inductive reactance that may fully or partially counteract the capacitive reactance of the decoupling capacitor. As a result, this approach can mitigate the performance degradation associated with resonance. In other words, by fully or partially cancelling the capacitive reactance of the decoupling capacitor, the resonant frequency of the parallel LC resonance is either substantially reduce or shifted out of the designed operational frequency band of the RF shunt switch and as a result, the negative impact of the resonance on the ON-resistance (Ron) of the RF shunt switch will be reduced or eliminated. According a first aspect of the present disclosure, a circuital arrangement is provided, comprising an integrated circuit (IC), the IC comprising: a shunt switch; a decoupling capacitance connecting a source terminal of the switch to a first pin of the IC; a storage capacitance disposed outside the IC and coupled to the first pin of the IC; a resonance-canceling inductance disposed outside the IC and in series with the storage capacitance; wherein: the storage capacitance acts as an alternating current (AC)-short circuit across an operational frequency band of the IC; the resonance-canceling inductance is configured to cancel or attenuate a parasitic resonance, by a combination of i) a series arrangement of a parasitic ground inductance inside the IC and a parasitic ground inductance outside the IC with ii) a parallel arrangement of the decoupling capacitance and a parasitic capacitance, the parasitic resonance to be canceled or reduced occurring at a frequency within an operational frequency band of the circuital arrangement. According to a second aspect of the present disclosure, a circuital arrangement is provided, comprising an integrated circuit (IC), the IC comprising: a shunt switch; a decoupling capacitance connecting a source terminal of the switch to a first pin of the IC; a storage capacitance disposed outside the IC and coupled to the first pin; a resonance-canceling inductance disposed inside the IC and in series with the decoupling capacitance; wherein: the storage capacitance acts as an alternating current (AC)-short circuit across an operational frequency band of the IC; the resonance-canceling inductance is configured to cancel or attenuate a parasitic resonance, by a combination of i) a series arrangement of a parasitic ground inductance inside the IC and a parasitic ground inductance outside the IC with ii) a parallel arrangement of the decoupling capacitance and a parasitic capacitance, the parasitic resonance to be canceled or reduced occurring at a frequency within an operational frequency band of the circuital arrangement. According to a third aspect of the present disclosure, a circuital arrangement is provided, comprising an integrated circuit (IC), the IC comprising: a shunt switch; a decoupling capacitance connecting a source terminal of the switch to a first pin of the IC; a storage capacitance disposed outside the IC and coupled to the first pin of the IC; a resistor disposed inside the IC and in series with the storage capacitance; wherein: the storage capacitance acts as an alternating current (AC)-short circuit across an operational frequency band of the IC; the resistor is configured to attenuate a parasitic resonance, by a combination of i) a series arrangement of a parasitic ground inductance inside the IC and a parasitic ground inductance outside the IC with ii) a parallel arrangement of the decoupling capacitance and a parasitic capacitance, by spreading the parasitic resonance across an operational frequency band of the circuital arrangement. According to a fourth aspect of the present disclosure, a method of canceling or attenuating a resonance generated in a radio frequency (RF) integrated circuit (IC) circuit is disclosed, the IC including: a shun