US-12622067-B2 - Integrated circuit for power clamping

US12622067B2US 12622067 B2US12622067 B2US 12622067B2US-12622067-B2

Abstract

An integrated circuit for power clamping is provided. The integrated circuit for power clamping is electrically coupled to an internal circuit of an integrated circuit through a power line and a ground line, and includes a switch, a first resistor, a capacitor, an inverter and a voltage detection circuit. The voltage detection circuit detects a voltage of the power line, and when the voltage of the power line exceeds a threshold value, the voltage detection circuit electrically connects a first node to the ground line, such that a low potential signal from the ground line is input to the input terminal of the inverter, and then the switch is turned on to form a discharge path.

Inventors

Jyun-Ren Chen
SHIH-HSIN LIAO
Po-Ching Lin
Tay-Her Tsaur

Assignees

REALTEK SEMICONDUCTOR CORP.

Dates

Publication Date: 20260505
Application Date: 20230504
Priority Date: 20220505

Claims (11)

1 . An integrated circuit for power clamping, electrically coupled to an internal circuit of another integrated circuit through a power line and a ground line, the integrated circuit for power clamping comprising: a switch electrically coupled between the power line and the ground line, the switch having a control terminal; wherein the switch is a first N-channel metal-oxide-semiconductor field-effect transistor (N-MOSFET); a first resistor electrically coupled between the power line and a first node; a capacitor electrically coupled between the first node and the ground line; an inverter electrically coupled between the first node and the control terminal of the switch, wherein an input terminal of the inverter is electrically coupled to the first node, and an output terminal of the inverter is electrically coupled to the control terminal of the switch; and a voltage detection circuit electrically coupled to the power line, the first node and the ground line, wherein the voltage detection circuit is configured to detect whether a voltage of the power line exceeds a threshold value, wherein when the voltage of the power line exceeds the threshold, the voltage detection circuit electrically couples the first node with the ground line, such that the input terminal of the inverter electrically coupled with the first node is pulled low to activate the switch and forming a discharge path in the switch; wherein the voltage detection circuit includes: a second N-MOSFET, wherein a drain of the second N-MOSFET is electrically coupled to the first node, a gate of the second N-MOSFET is electrically coupled to a second node, and a source of the second N-MOSFET is electrically coupled to the ground line; an impedance component electrically coupled between the second node and the ground line; and a plurality of third N-MOSFETs being connected in series between the power line and the second node.
2 . The integrated circuit for power clamping according to claim 1 , wherein a drain of the first N-MOSFET is electrically coupled to the power line, a source of the first N-MOSFET is electrically coupled to the ground line, and a gate of the first N-MOSFET is taken as the control terminal electrically coupled to the output terminal of the inverter.
3 . The integrated circuit for power clamping according to claim 2 , wherein the threshold value is determined according to a voltage defined by the integrated circuit for electrical overstress (EOS) protection.
4 . The integrated circuit for power clamping according to claim 1 , wherein the impedance component is a second resistor.
5 . The integrated circuit for power clamping according to claim 4 , wherein the inverter is a static complementary metal-oxide-semiconductor (CMOS) inverter, and includes: a first P-MOSFET, wherein a source of the first P-MOSFET is electrically coupled to the power line, and a gate of the first P-MOSFET is electrically coupled to the first node, and a drain of the first P-MOSFET is electrically coupled to the gate of the first N-MOSFET through a third node; and a fourth N-MOSFET, wherein a source of the fourth N-MOSFET is electrically coupled to the ground line, and a gate of the third N-MOSFET is electrically coupled to the gate of the first P-MOSFET, and a drain of the fourth N-MOSFET is electrically coupled to the third node.
6 . An integrated circuit for power clamping, electrically coupled to an internal circuit of another integrated circuit through a power line and a ground line, the integrated circuit for power clamping comprising: a switch electrically coupled between the power line and the ground line, the switch having a control terminal; wherein the switch is a first N-channel metal-oxide-semiconductor field-effect transistor (N-MOSFET); a first resistor electrically coupled between the power line and a first node; a capacitor electrically coupled between the first node and the ground line; an inverter electrically coupled between the first node and the control terminal of the switch, wherein an input terminal of the inverter is electrically coupled to the first node, and an output terminal of the inverter is electrically coupled to the control terminal of the switch; and a voltage detection circuit electrically coupled to the power line, the first node and the ground line, wherein the voltage detection circuit is configured to detect whether a voltage of the power line exceeds a threshold value, wherein when the voltage of the power line exceeds the threshold, the voltage detection circuit electrically couples the first node with the ground line, such that the input terminal of the inverter electrically coupled with the first node is pulled low to activate the switch and forming a discharge path in the switch; wherein the voltage detection circuit further includes: a second N-MOSFET, wherein a drain of the second N-MOSFET is electrically coupled to the first node, a gate of the second N-MOSFET is electrically coupled to a second node, and a source of the second N-MOSFET is electrically coupled to the ground line; a first P-MOSFET, wherein a drain of the first P-MOSFET is electrically coupled to the second node, a source of the first P-MOSFET is electrically coupled to the ground line, and a gate of the first P-MOSFET is electrically coupled to the source of the first P-MOSFET; and a threshold setting circuit coupled between the power line and the second node.
7 . The integrated circuit for power clamping according to claim 6 , wherein the inverter is a static complementary metal-oxide-semiconductor (CMOS) inverter, and includes: a second P-MOSFET, wherein a source of the second P-MOSFET is electrically coupled to the power line, a gate of the second P-MOSFET is electrically coupled to the first node, and a drain of the second P-MOSFET is electrically coupled to the gate of the first N-MOSFET through a third node; and a third N-MOSFET, wherein a source of the third N-MOSFET is electrically coupled to the ground line, a gate of the third N-MOSFET is electrically coupled to the gate of the second P-MOSFET, and a drain of the third N-MOSFET is electrically coupled to the third node.
8 . The integrated circuit for power clamping according to claim 6 , wherein the threshold setting circuit is a plurality of diodes connected in series.
9 . An integrated circuit for power clamping, electrically coupled to an internal circuit of another integrated circuit through a power line and a ground line, the integrated circuit for power clamping comprising: a switch electrically coupled between the power line and the ground line, the switch having a control terminal; wherein the switch is a first N-channel metal-oxide-semiconductor field-effect transistor (N-MOSFET); a first resistor electrically coupled between the power line and a first node; a capacitor electrically coupled between the first node and the ground line; an inverter electrically coupled between the first node and the control terminal of the switch, wherein an input terminal of the inverter is electrically coupled to the first node, and an output terminal of the inverter is electrically coupled to the control terminal of the switch; and a voltage detection circuit electrically coupled to the power line, the first node and the ground line, wherein the voltage detection circuit is configured to detect whether a voltage of the power line exceeds a threshold value, wherein when the voltage of the power line exceeds the threshold, the voltage detection circuit electrically couples the first node with the ground line, such that the input terminal of the inverter electrically coupled with the first node is pulled low to activate the switch and forming a discharge path in the switch; wherein the voltage detection circuit further includes: a second N-MOSFET, wherein a drain of the second N-MOSFET is electrically coupled to the first node, a gate of the second N-MOSFET is electrically coupled to a second node, and a source of the second N-MOSFET is electrically coupled to the ground line; a third N-MOSFET, wherein a drain of the third N-MOSFET is electrically coupled to the second node, a source of the third N-MOSFET is electrically coupled to the ground line, and a gate of the third N-MOSFET is electrically coupled to the power line; and a threshold setting circuit coupled between the power line and the second node.
10 . The integrated circuit for power clamping according to claim 9 , wherein the inverter is a static complementary metal-oxide-semiconductor (CMOS) inverter, and includes: a first P-MOSFET, wherein a source of the first P-MOSFET is electrically coupled to the power line, a gate of the first P-MOSFET is electrically coupled to the first node, and a drain of the first P-MOSFET is electrically coupled to the gate of the first N-MOSFET through a third node; and a fourth N-MOSFET, wherein a source of the fourth N-MOSFET is electrically coupled to the ground line, a gate of the third N-MOSFET is electrically coupled to the gate of the first P-MOSFET, and a drain of the fourth N-MOSFET is electrically coupled to the third node.
11 . The integrated circuit for power clamping according to claim 9 , wherein the threshold setting circuit is a plurality of diodes connected in series.

Description

CROSS-REFERENCE TO RELATED PATENT APPLICATION This application claims the benefit of priority to Taiwan Patent Application No. 111116888, filed on May 5, 2022. The entire content of the above identified application is incorporated herein by reference. Some references, which may include patents, patent applications and various publications, may be cited and discussed in the description of this disclosure. The citation and/or discussion of such references is provided merely to clarify the description of the present disclosure and is not an admission that any such reference is “prior art” to the disclosure described herein. All references cited and discussed in this specification are incorporated herein by reference in their entireties and to the same extent as if each reference was individually incorporated by reference. FIELD OF THE DISCLOSURE The present disclosure relates to an integrated circuit (IC), and more particularly to an integrated circuit for power clamping capable of forming a discharge path for an electrical overstress (EOS) event. BACKGROUND OF THE DISCLOSURE An integrated circuit (IC) may be provided with a power clamping circuit to form a discharge path for electrostatic discharge (ESD), so as to prevent an ESD surge current from flowing into an internal circuit of the IC and protect the IC from burning out. However, an electrical overstress (EOS) event (also referred to as a system ESD) may occur during normal operation of the IC, and the EOS events typically last in an order of microseconds compared to ESD events, which typically last in an order of nanoseconds. Therefore, it is difficult for the existing integrated circuit for power clamping to form a discharge path for the EOS event to prevent the EOS surge current from flowing into the internal circuit of the IC and burning the IC out. SUMMARY OF THE DISCLOSURE In response to the above-referenced technical inadequacies, the present disclosure provides an integrated circuit for power clamping that can form a discharge path for an electrical overstress (EOS) event, so as to prevent an EOS surge current from flowing into an internal circuit of an IC and protecting the IC from burning out. In one aspect, the present disclosure provides an integrated circuit for power clamping. The integrated circuit for power clamping is electrically coupled to an internal circuit of another integrated circuit through a power line and a ground line, and the integrated circuit for power clamping includes a switch, a first resistor, a capacitor, an inverter and a voltage detection circuit. The switch is electrically coupled between the power line and the ground line. The first resistor is electrically coupled between the power line and the first node. The capacitor is electrically coupled between the first node and the ground line. The inverter is electrically coupled between the first node and the control terminal of the switch. An input terminal of the inverter is electrically coupled to the first node, and an output terminal of the inverter is electrically coupled to the control terminal of the switch. The voltage detection circuit is electrically coupled to the power line, the first node and the ground line, and is configured to detect a voltage of the power line. In response to detecting that the voltage of the power line exceeds a threshold value, the voltage detection circuit is further configured to electrically connect the first node to the ground line, such that the input terminal of the inverter electrically coupled with the first node is pulled low to activate the switch and forming a discharge path in the switch. These and other aspects of the present disclosure will become apparent from the following description of the embodiment taken in conjunction with the following drawings and their captions, although variations and modifications therein may be affected without departing from the spirit and scope of the novel concepts of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS The described embodiments may be better understood by reference to the following description and the accompanying drawings, in which: FIG. 1 is a schematic diagram of an integrated circuit for power clamping according to one embodiment of the present disclosure; FIG. 2 is a schematic diagram of a voltage detection circuit according to a first embodiment of the present disclosure; FIG. 3 is a schematic diagram of a voltage detection circuit according to a second embodiment of the present disclosure; FIG. 4 is a schematic diagram of a voltage detection circuit according to a third embodiment of the present disclosure; FIG. 5 is a schematic diagram of a voltage detection circuit according to a fourth embodiment of the present disclosure; and FIG. 6 is a schematic diagram of a voltage detection circuit according to a fifth embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS The present disclosure is more particularly described in the following