US-12622078-B2 - Chip package structure

US12622078B2US 12622078 B2US12622078 B2US 12622078B2US-12622078-B2

Abstract

A chip package structure includes a substrate, a chip, a light-permeable element, a first anti-reflective layer, and an adhesive element. The chip is disposed on the substrate. The light-permeable element is disposed above the chip. The light-permeable element has a first surface and a second surface opposite to each other, and the first surface faces the chip. The first anti-reflective layer covers at least part of the first surface. The adhesive element is connected between the chip and the light-permeable element, and the adhesive element separates the chip and the light-permeable element. The adhesive element and the first anti-reflective layer are not in contact with each other.

Inventors

Jui-Hung Hsu
Li-Chun Hung
Chien-Chen Lee

Assignees

TONG HSING ELECTRONIC INDUSTRIES, LTD.

Dates

Publication Date: 20260505
Application Date: 20230703
Priority Date: 20230111

Claims (10)

1 . A chip package structure, comprising: a substrate; a chip disposed on the substrate; a light-permeable element disposed above the chip, wherein the light-permeable element includes a first surface and a second surface that are opposite to each other, and the first surface faces the chip; a first anti-reflective layer covering at least part of the first surface; a second anti-reflective layer covering the second surface; and an adhesive element connected between the chip and the light-permeable element, wherein the adhesive element separates the chip and the light-permeable element, and the adhesive element and the first anti-reflective layer are not in contact with each other; wherein the first anti-reflective layer forms a window, the adhesive element includes a first end and a second end, the first end is disposed in the window and directly connected to the first surface, and the second surface is connected to a surface of the chip; wherein a gap is formed between an edge of the window and the adhesive element, the adhesive element has an average width, and a width of the gap ranges from one-tenth to one-sixth of the average width.
2 . The chip package structure according to claim 1 , wherein a thickness of each of the first anti-reflective layer and the second anti-reflective layer ranges from 200 nm and 1000 nm.
3 . The chip package structure according to claim 1 , further including a plurality of metal wires, and the plurality of metal wires are electrically connected between the chip and the substrate.
4 . The chip package structure according to claim 3 , further comprising an encapsulation colloid disposed on the substrate, wherein the chip, the adhesive element, the light-permeable element, the first anti-reflective layer, and the plurality of metal wires are embedded within the encapsulation colloid, and the second surface of the light-permeable element is exposed from the encapsulation colloid.
5 . A chip package structure, comprising: a substrate; a chip disposed on the substrate; a light-permeable element disposed above the chip, wherein the light-permeable element includes a first surface and a second surface that are opposite to each other, and the first surface faces the chip; a first anti-reflective layer covering at least part of the first surface; a second anti-reflective layer covering the second surface; a shielding layer formed at an inner side of the first surface; and an adhesive element connected between the chip and the light-permeable element, wherein the adhesive element separates the chip and the light-permeable element, and the adhesive element and the first anti-reflective layer are not in contact with each other; wherein the first anti-reflective layer forms a window, the adhesive element includes a first end and a second end, the first end is disposed within the window and directly connected to an outer side of the first surface, such that the adhesive element and the shielding layer are respectively located at two opposite sides of the first surface, and the second end is connected to a surface of the chip.
6 . The chip package structure according to claim 5 , wherein the shielding layer and the first anti-reflective layer do not overlap with each other.
7 . The chip package structure according to claim 5 , wherein the chip includes an image sensing region, and an orthogonal projection of the shielding layer that is projected onto the first surface and an orthogonal projection of the image sensing region that is projected onto the first surface do not overlap with each other.
8 . A chip package structure, comprising: a substrate; a chip disposed on the substrate; a light-permeable element disposed above the chip, wherein the light-permeable element includes a first surface and a second surface that are opposite to each other, and the first surface faces the chip; a first anti-reflective layer covering a part of the first surface, wherein the first anti-reflective layer forms a window; a second anti-reflective layer covering the second surface; a shielding layer covering another part of the first surface and disposed within the window, wherein the shielding layer surrounds and is connected to the first ani-reflective layer; and an adhesive element connected between the chip and the light-permeable element, wherein the adhesive element separates the chip and the light-permeable element, and the adhesive element and the first anti-reflective layer are not in contact with each other; wherein the adhesive element includes a first end and a second end, the first end is directly connected to the shielding layer, and the second end is connected to a surface of the chip.
9 . The chip package structure according to claim 8 , wherein the shielding layer and the first anti-reflective layer do not overlap with each other.
10 . The chip package structure according to claim 8 , wherein the chip includes an image sensing region, and an orthogonal projection of the shielding layer that is projected onto the first surface and an orthogonal projection of the image sensing region that is projected onto the first surface do not overlap with each other.

Description

CROSS-REFERENCE TO RELATED PATENT APPLICATION This application claims the benefit of priority to Taiwan Patent Application No. 112101116, filed on Jan. 11, 2023. The entire content of the above identified application is incorporated herein by reference. Some references, which may include patents, patent applications and various publications, may be cited and discussed in the description of this disclosure. The citation and/or discussion of such references is provided merely to clarify the description of the present disclosure and is not an admission that any such reference is “prior art” to the disclosure described herein. All references cited and discussed in this specification are incorporated herein by reference in their entireties and to the same extent as if each reference was individually incorporated by reference. FIELD OF THE DISCLOSURE The present disclosure relates to a chip package structure, and more particularly to a chip package structure capable of improving structural strength. BACKGROUND OF THE DISCLOSURE In the conventional chip-level sensor package structure, such as a complementary metal oxide semiconductor (CMOS), a glass element used as an upper cover is fixed on a substrate by an adhesive. The adhesive acts as a supporting wall structure that hermetically surrounds a sensing chip. However, an upper surface and a lower surface of the glass element are respectively coated with an anti-reflection film, and the adhesive is directly adhered to the anti-reflection film. The anti-reflection film is relatively fragile, so as to be easily torn by the adhesive during the curing process. In addition, any crack existing in the adhesive will extend from the interface between the adhesive and the anti-reflection film to the anti-reflection film, thereby causing the anti-reflection film to peel off. Therefore, how to improve structural strength through the improvement of the chip packaging structure and overcome the above-mentioned inadequacy has become an important issue to be addressed in the related art. SUMMARY OF THE DISCLOSURE In response to the above-referenced technical inadequacy, the present disclosure provides a chip package structure. In one aspect, the present disclosure provides a chip package structure, which includes a substrate, a chip, a light-permeable element, a first anti-reflection layer, and an adhesive element. The chip is disposed on the substrate. The light-permeable element is disposed above the chip. The light-permeable element includes a first surface and a second surface that are opposite to each other, and the first surface faces the chip. The first anti-reflective layer covers at least part of the first surface. The second anti-reflective layer covers the second surface. The adhesive element is connected between the chip and the light-permeable element, the adhesive element separates the chip and the light-permeable element, and the adhesive element and the first anti-reflective layer are not in contact with each other. Therefore, in the chip package structure provided by the present disclosure, by virtue of “the first anti-reflective layer covering at least part of the first surface,” and “the adhesive element and the first anti-reflective layer being not in contact with each other,” the first anti-reflective layer can avoid being torn and peeled off by the adhesive element, and an overall structural strength of the chip package structure can be improved. These and other aspects of the present disclosure will become apparent from the following description of the embodiment taken in conjunction with the following drawings and their captions, although variations and modifications therein may be affected without departing from the spirit and scope of the novel concepts of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS The described embodiments may be better understood by reference to the following description and the accompanying drawings, in which: FIG. 1 is a schematic exploded view of a chip package structure according to a first embodiment of the present disclosure; FIG. 2 is a schematic enlarged view of part II of FIG. 1; FIG. 3 is a schematic exploded view of a chip package structure according to a second embodiment of the present disclosure; FIG. 4 is a schematic enlarged view of part IV of FIG. 3; FIG. 5 is a schematic exploded view of a chip package structure according to a third embodiment of the present disclosure; and FIG. 6 is a schematic enlarged view of part VI of FIG. 5. DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS The present disclosure is more particularly described in the following examples that are intended as illustrative only since numerous modifications and variations therein will be apparent to those skilled in the art. Like numbers in the drawings indicate like components throughout the views. As used in the description herein and throughout the claims that follow, unless the context clearly dictates otherwise, the meaning of “a,” “an” a