US-12622080-B1 - Front-end and back-end processing method and device for integrated sensor array using isolation structures

Abstract

An integrated sensor array device and method. The method includes providing a partially completed semiconductor substrate having a material stack used to form a sensor array device with a plurality of device regions. One or more isolation trench regions separating the device regions can be formed in a front-end isolation process during the formation of the device regions or in a back-end isolation process following a bonding process to integrate the sensor array device to an integrated circuit (IC) device. Prior to the front-end or back-end processing, metal interconnect materials within a passivation material can be formed via a planarization process to provide connection to n-type and p-type contact regions of the sensor array device. The resulting planarized sensor array device can then be bonded to the IC device, and a plurality of surface relief structures can be formed overlying a backside surface region of the planarized sensor array device.

Inventors

• Jonathan KLAMKIN
• Bowen SONG
• Bei Shi

Assignees

• Aeluma, Inc.

Dates

Publication Date

20260505

Application Date

20230717

Claims (20)

1. 1 . A method for fabricating an integrated sensor array device, the method comprising: providing a partially completed semiconductor substrate comprising a silicon substrate, a buffer material overlying the silicon substrate, an n-type semiconductor material overlying the silicon substrate, a transition material overlying the n-type semiconductor material, and an unintentionally doped (UID) optically transparent semiconductor material overlying the transition material; forming a first dielectric material overlying at least a portion of the UID optically transparent semiconductor material; removing one or more portions of the UID optically transparent material and the transition material to form one or more isolation trench regions and a recessed region, the one or more isolation trench regions separating a plurality of device regions; forming a first dielectric material overlying the UID optically transparent material, the transition material, and the one or more isolation trench regions; removing a portion of the first dielectric material within the recessed region to form an n-type contact region; forming a second dielectric material overlying the first dielectric material, the one or more isolation trench regions, the recessed region, and the n-type contact region; removing a portion of the second dielectric material and the first dielectric material overlying the UID optically transparent semiconductor material within each device region to form a first contact trench region exposing a portion of the UID optically transparent semiconductor material of each device region; forming a p-type contact region within a portion of the UID optically transparent semiconductor material of each device region; forming a first metal contact material within the first contact trench region overlying the p-type contact region of each device region; removing a portion of the second dielectric material and the first dielectric material overlying the n-type contact region to form a second contact trench region; forming a second metal contact material overlying the n-type contact region within the second contact trench region; forming a third dielectric material overlying the second dielectric material, the first metal contact materials, and the second metal contact material; removing a plurality of first portions of the third dielectric material to define a first bond pad region overlying the first metal contact material of each device region; removing a second portion of the third dielectric material to define a second bond pad region overlying the second metal contact material; forming a first bond pad within the first bond pad region overlying the first metal contact material of each device region; and forming a second bond pad within the second bond pad region overlying the second metal contact material forming a first metal interconnect material overlying each first bond pad; forming a passivation material overlying the first metal interconnect materials, the first bond pads, and the third dielectric material; removing one or more portions of the passivation material using a planarization process to smooth the passivation material and expose the first metal interconnect materials, resulting in a planarized sensor array device; and bonding the planarized sensor array device overlying an integrated circuit (IC) device such that the first metal interconnect materials are coupled to a plurality of first IC bond pads of the IC device and the second metal interconnect material is coupled to a second IC bond pad of the IC device.
2. 2 . The method of claim 1 wherein forming the one or more isolation trench regions and the recessed region comprises: removing one or more portions of UID optically transparent material using an inductively coupled plasma (ICP) etching process to form the one or more isolation trench regions and the recessed region; removing one or more portions of the UID optically transparent material underlying the one or more isolation trench regions and the recessed region using a spacer patterning process to extend the one or more isolation trench regions and the recessed region such that the underlying transition material is exposed; and removing one or more portions of the transition material underlying the one or more isolation trench regions and the recessed region using a mask process.
3. 3 . The method of claim 1 further comprising removing a portion of the second dielectric material and the first dielectric material overlying each of the one or more isolation trench regions to form a metal isolation trench region; and forming a metal fill material within each metal isolation trench region.
4. 4 . The method of claim 1 further comprising forming a plurality of surface relief structures overlying a backside surface region of the silicon substrate, wherein the surface relief structures includes microlenses, optical diffusers, or diffraction gratings.
5. 5 . The method of claim 1 further comprising removing the silicon substrate using a grinding, polishing, or etching process; removing the buffer material using a grinding, polishing, or etching process; forming a plurality of surface relief structures overlying a frontside surface region of an optics silicon substrate, wherein the surface relief structures includes microlenses, optical diffusers, or diffraction gratings; and bonding a backside surface region of the optics silicon substrate to the n-type semiconductor material.
6. 6 . The method of claim 1 further comprising removing one or more portions of the bonded planarized sensor array device overlying the second metal interconnect to form a backside contact trench region; forming a backside metal fill material within the backside contact trench region; and forming a backside bond pad overlying the backside contact trench region and a portion of the silicon substrate, the backside bond pad being coupled to the second metal interconnect through the backside metal fill material.
7. 7 . The method of claim 1 wherein the bonded IC device is spatially oriented overlying the bonded planarized sensor array device; and further comprising removing one or more portions of the bonded IC device from overlying the second IC bond pad to form a backside contact trench region; forming a backside metal fill material within the backside contact trench region; and forming a backside bond pad overlying the backside contact trench region and a portion of an IC silicon substrate of the bonded IC device, the backside bond pad being coupled to the second IC bond pad through the backside metal fill material.
8. 8 . The method of claim 1 wherein the bonded IC device is spatially oriented overlying the bonded planarized sensor array device; and further comprising removing one or more portions of the bonded IC device from overlying the second IC bond pad to form a backside contact trench region; forming a backside metal fill material within the backside contact trench region; and forming a backside bond pad overlying the backside contact trench region and a portion of an IC silicon substrate of the bonded IC device, the backside bond pad being coupled to the second IC bond pad through the backside metal fill material.
9. 9 . A method for fabricating an integrated sensor array device, the method comprising: providing a partially completed semiconductor substrate comprising a silicon substrate, a buffer material overlying the silicon substrate, an n-type semiconductor material overlying the silicon substrate, a transition material overlying the n-type semiconductor material, and an unintentionally doped (UID) optically transparent semiconductor material overlying the transition material; forming a first dielectric material overlying at least a portion of the UID optically transparent semiconductor material; removing one or more portions of the UID optically transparent material and the transition material to form one or more isolation trench regions and a recessed region, the one or more isolation trench regions separating a plurality of device regions; forming a first dielectric material overlying the UID optically transparent material, the transition material, and the one or more isolation trench regions; removing a portion of the first dielectric material within the recessed region to form an n-type contact region; forming a second dielectric material overlying the first dielectric material, the one or more isolation trench regions, the recessed region, and the n-type contact region; removing a portion of the second dielectric material and the first dielectric material overlying the UID optically transparent semiconductor material within each device region to form a first contact trench region exposing a portion of the UID optically transparent semiconductor material of each device region; forming a p-type contact region within a portion of the UID optically transparent semiconductor material of each device region; forming a first metal contact material within the first contact trench region overlying the p-type contact region of each device region; removing a portion of the second dielectric material and the first dielectric material overlying the n-type contact region to form a second contact trench region; forming a second metal contact material overlying the n-type contact region within the second contact trench region; forming a passivation layer overlying the second dielectric material and the first metal contact material of each device region; removing a portion of the passivation layer overlying the first metal contact material of each device region to form an interconnect footprint cavity overlying the first metal contact material of each device region; forming a metal interconnect layer overlying the passivation layer and within the interconnect footprint cavity of each device region; and removing one or more portions of the metal interconnect layer using a planarization process to form a metal interconnect material within the interconnect footprint cavity of each device region, resulting in a planarized sensor array device; and bonding the planarized sensor array device overlying an integrated circuit (IC) device such that the first metal interconnect materials are coupled to a plurality of IC bond pads of the IC device.
10. 10 . The method of claim 9 wherein forming the one or more isolation trench regions and the recessed region comprises: removing one or more portions of UID optically transparent material using an inductively coupled plasma (ICP) etching process to form the one or more isolation trench regions and the recessed region; removing one or more portions of the UID optically transparent material underlying the one or more isolation trench regions and the recessed region using a spacer patterning process to extend the one or more isolation trench regions and the recessed region such that the underlying transition material is exposed; and removing one or more portions of the transition material underlying the one or more isolation trench regions and the recessed region using a mask process.
11. 11 . The method of claim 9 further comprising removing a portion of the second dielectric material and the first dielectric material overlying each of the one or more isolation trench regions to form a metal isolation trench region; and forming a metal fill material within each metal isolation trench region.
12. 12 . The method of claim 9 further comprising forming a plurality of surface relief structures overlying a backside surface region of the silicon substrate, wherein the surface relief structures includes microlenses, optical diffusers, or diffraction gratings.
13. 13 . The method of claim 9 further comprising removing the silicon substrate using a grinding, polishing, or etching process; removing the buffer material using a grinding, polishing, or etching process; forming a plurality of surface relief structures overlying a frontside surface region of an optics silicon substrate, wherein the surface relief structures includes microlenses, optical diffusers, or diffraction gratings; and bonding a backside surface region of the optics silicon substrate to the n-type semiconductor material.
14. 14 . The method of claim 9 further comprising removing one or more portions of the bonded planarized sensor array device overlying the second metal interconnect to form a backside contact trench region; forming a backside metal fill material within the backside contact trench region; and forming a backside bond pad overlying the backside contact trench region and a portion of the silicon substrate, the backside bond pad being coupled to the second metal interconnect through the backside metal fill material.
15. 15 . A method for fabricating an integrated sensor array device, the method comprising: providing a partially completed semiconductor substrate comprising a silicon substrate, a buffer material overlying the silicon substrate, an n-type semiconductor material overlying the silicon substrate, a transition material overlying the n-type semiconductor material, and an unintentionally doped (UID) optically transparent semiconductor material overlying the transition material; forming a first dielectric material overlying at least a portion of the UID optically transparent semiconductor material; removing one or more portions of the UID optically transparent material and the transition material to form a recessed region; forming a first dielectric material overlying the UID optically transparent material and the transition material; removing a portion of the first dielectric material within the recessed region to form an n-type contact region; forming a second dielectric material overlying the first dielectric material, the recessed region, and the n-type contact region; removing a plurality of portions of the second dielectric material and the first dielectric material overlying the UID optically transparent semiconductor material to form a plurality of first contact trench regions, each first contact trench region exposing a portion of the UID optically transparent semiconductor material and defining a device region; forming a p-type contact region within a portion of the UID optically transparent semiconductor material of each device region; forming a first metal contact material within the first contact trench region overlying the p-type contact region of each device region; removing a portion of the second dielectric material and the first dielectric material overlying the n-type contact region to form a second contact trench region; forming a second metal contact material overlying the n-type contact region within the second contact trench region; forming a third dielectric material overlying the second dielectric material, the first metal contact materials, and the second metal contact material; removing a plurality of first portions of the third dielectric material to define a first bond pad region overlying the first metal contact material of each device region; removing a second portion of the third dielectric material to define a second bond pad region overlying the second metal contact material; forming a first bond pad within the first bond pad region overlying the first metal contact material of each device region; and forming a second bond pad within the second bond pad region overlying the second metal contact material forming a first metal interconnect material overlying each first bond pad; forming a passivation material overlying the first metal interconnect materials, the first bond pads, and the third dielectric material; removing one or more portions of the passivation material using a planarization process to smooth the passivation material and expose the first metal interconnect materials, resulting in a planarized sensor array device; bonding the planarized sensor array device overlying an integrated circuit (IC) device such that the first metal interconnect materials are coupled to a plurality of first IC bond pads of the IC device and the second metal interconnect material is coupled to a second IC bond pad of the IC device; removing a plurality of portions of the bonded planarized sensor array device overlying the bonded IC device to form a backside isolation trench region spatially configured between each device region; and forming a backside metal fill material within each backside isolation trench region.
16. 16 . The method of claim 15 further comprising forming a plurality of surface relief structures overlying a backside surface region of the silicon substrate, wherein the surface relief structures includes microlenses, optical diffusers, or diffraction gratings.
17. 17 . The method of claim 15 further comprising removing the silicon substrate using a grinding, polishing, or etching process; removing the buffer material using a grinding, polishing, or etching process; forming a plurality of surface relief structures overlying a frontside surface region of an optics silicon substrate, wherein the surface relief structures includes microlenses, optical diffusers, or diffraction gratings; and bonding a backside surface region of the optics silicon substrate to the n-type semiconductor material.
18. 18 . The method of claim 15 further comprising removing one or more portions of the bonded planarized sensor array device overlying the second metal interconnect to form a backside contact trench region; forming a backside metal fill material within the backside contact trench region; and forming a backside bond pad overlying the backside contact trench region and a portion of the silicon substrate, the backside bond pad being coupled to the second metal interconnect through the backside metal fill material.
19. 19 . The method of claim 15 wherein the bonded IC device is spatially oriented overlying the bonded planarized sensor array device; and further comprising removing one or more portions of the bonded IC device from overlying the second IC bond pad to form a backside contact trench region; forming a backside metal fill material within the backside contact trench region; and forming a backside bond pad overlying the backside contact trench region and a portion of an IC silicon substrate of the bonded IC device, the backside bond pad being coupled to the second IC bond pad through the backside metal fill material.
20. 20 . A method for fabricating an integrated sensor array device, the method comprising: providing a partially completed semiconductor substrate comprising a silicon substrate, a buffer material overlying the silicon substrate, an n-type semiconductor material overlying the silicon substrate, a transition material overlying the n-type semiconductor material, and an unintentionally doped (UID) optically transparent semiconductor material overlying the transition material; forming a first dielectric material overlying at least a portion of the UID optically transparent semiconductor material; removing one or more portions of the UID optically transparent material and the transition material to form a recessed region; forming a first dielectric material overlying the UID optically transparent material and the transition material; removing a portion of the first dielectric material within the recessed region to form an n-type contact region; forming a second dielectric material overlying the first dielectric material, the recessed region, and the n-type contact region; removing a plurality of portions of the second dielectric material and the first dielectric material overlying the UID optically transparent semiconductor material to form a plurality of first contact trench regions, each first contact trench region exposing a portion of the UID optically transparent semiconductor material and defining a device region; forming a p-type contact region within a portion of the UID optically transparent semiconductor material of each device region; forming a first metal contact material within the first contact trench region overlying the p-type contact region of each device region; removing a portion of the second dielectric material and the first dielectric material overlying the n-type contact region to form a second contact trench region; forming a second metal contact material overlying the n-type contact region within the second contact trench region; forming a passivation layer overlying the second dielectric material and the first metal contact material of each device region; removing a portion of the passivation layer overlying the first metal contact material of each device region to form an interconnect footprint cavity overlying the first metal contact material of each device region; forming a metal interconnect layer overlying the passivation layer and within the interconnect footprint cavity of each device region; and removing one or more portions of the metal interconnect layer using a planarization process to form a metal interconnect material within the interconnect footprint cavity of each device region, resulting in a planarized sensor array device; bonding the planarized sensor array device overlying an integrated circuit (IC) device such that the first metal interconnect materials are coupled to a plurality of IC bond pads of the IC device; removing a plurality of portions of the bonded planarized sensor array device overlying the bonded IC device to form a backside isolation trench region spatially configured between each device region; and forming a backside metal fill material within each backside isolation trench region.

Description

CROSS-REFERENCES TO RELATED APPLICATIONS N/A BACKGROUND OF THE INVENTION Electronics have proliferated over the years. These devices rely on miniature chips made from semiconductor materials such as Silicon (Si). These materials are also used to make sensing devices that can capture images of scenes. Si is widely used because it is an abundant material and Si semiconductor manufacturing is extremely mature due to the investments made in the electronics industry. A common technology process is called complementary metal oxide semiconductor, or “CMOS.” The CMOS technology was developed for manufacturing integrated circuits but is now used for image sensors. Such image sensors are called CMOS image sensors. Often times, such CMOS image sensors are manufactured using high-volume manufacturing with 12-inch Si wafers. Despite the advances with CMOS image sensors, limitations or drawbacks exist. For example, CMOS image sensors have limitations in the detectable wavelength range. Additionally, such CMOS image sensors suffer from poor sensitivity at longer wavelengths within the detectable wavelength range. These and other limitations may also exist. From the above, it is desired that industry develop improved sensing devices. BRIEF SUMMARY OF THE INVENTION The present invention is generally related to electronic devices. More specifically, the present invention provides techniques related to sensor devices and sensor arrays using semiconductor materials on Si, along with subsequent circuit fabrication and integration methods. Merely by way of example, the present invention can be applied to various applications including image sensing, range finding, including LIDAR, among others, but it will be recognized that there are many other applications. According to various examples, the present invention provides for methods of fabricating an integrated sensor array device, as well as the resulting devices. The methods include providing a partially completed semiconductor substrate and forming an overlying first dielectric material. This partially completed substrate includes at least a silicon substrate, a buffer material overlying the silicon substrate, an n-type semiconductor material overlying the silicon substrate, a transition material overlying the n-type semiconductor material, and an unintentionally doped (UID) optically transparent semiconductor material overlying the transition material. A portion of the first and second dielectric materials overlying the UID optically transparent semiconductor within each device can be removed to form a first contact trench region exposing a portion of the UID optically transparent semiconductor material of each device region, and then a p-type contact region is formed within a portion of the UID optically transparent semiconductor material. Depending on the application, a plurality of device regions can be separated using front-end trench isolation, back-end trench isolation, or a combination thereof. In the case of front-end trench isolation, at least one or more portions of the UID optically transparent material and the transition material are removed to form one or more isolation trench regions separating a plurality of device regions. Also, a recessed region is formed along with the isolation trench regions, and a portion of the first dielectric material within the recessed region can be removed to form an n-type contact region. Then, a second dielectric material is formed overlying the first dielectric material, the one or more isolation trench regions, the recessed region, and the n-type contact region. Further, metal isolation trench regions with metal fill materials can be formed within the trench isolation regions and the second dielectric material. The method also includes forming a first metal contact material within the first contact trench region overlying the p-type contact region of each device region. Similarly, a portion of these dielectric materials can be removed overlying the n-type contact region to form a second contact trench region. A second metal contact material can be formed overlying the n-type contact region within the second contact trench region, and a third dielectric material can be formed overlying the second dielectric material, the first metal contact materials, and the second metal contact materials. The method can also include various planarization steps to prepare the sensor array device for integration with another integrated circuit (IC) device, such as a read-out integrated circuit (ROIC) device. In an example, a plurality of first portions of the third dielectric material can be removed to define a first bond pad region overlying the first metal contact material of each device region, and a second portion of the third dielectric material can be removed to define a second bond pad region overlying the second metal contact material. A first bond pad is formed within the first bond pad region of each device region, and a second bond pad