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US-12622081-B2 - Sensor device and electronic apparatus

US12622081B2US 12622081 B2US12622081 B2US 12622081B2US-12622081-B2

Abstract

There are provided a sensor device and an electronic apparatus that are capable of reducing the occurrence of defects. The sensor device includes: a first substrate; a second substrate provided on a side of one surface of the first substrate; an insulating first film that is provided on the side of the one surface and covers the second substrate; and a second film that is formed of a material different from that of the first film and provided at a position facing the first substrate across the first film. The second substrate and the first film are intermixed in a first layer and the first film and the second film are intermixed in a second layer. The second film is present outside the second substrate in plan view from a direction normal to the one surface.

Inventors

  • Akihisa Sakamoto

Assignees

  • SONY SEMICONDUCTOR SOLUTIONS CORPORATION

Dates

Publication Date
20260505
Application Date
20210811
Priority Date
20200824

Claims (17)

  1. 1 . A sensor device, comprising: a first substrate comprising an image sensor; a second substrate comprising a logic circuit for processing signals from the image sensor, the second substrate being provided on a first surface side of the first substrate; a first insulating film that is provided on the first surface side of the first substrate and that covers the second substrate; and a second insulating film that is formed of a material different from that of the first insulating film and that is disposed in the first insulating film on a side of the first insulating film opposite the second substrate, wherein the second insulating film does not overlap the second substrate in a plan view.
  2. 2 . The sensor device according to claim 1 , further comprising wherein a surface of the second substrate and a surface of the second insulating film that are closest to one another are separated by part of the first insulating film.
  3. 3 . The sensor device according to claim 1 , further comprising: a support substrate in contact with the first insulating film and the second insulating film.
  4. 4 . The sensor device according to claim 1 , further comprising: a third substrate that is disposed on the side of the first surface side of the first substrate, wherein the first insulating film covers the third substrate, and wherein the second insulating film does not overlap with the third substrate in the plan view.
  5. 5 . The sensor device according to claim 1 , wherein the first substrate is part of a set of stacked substrates stacked in a thickness direction.
  6. 6 . The sensor device according to claim 1 , further comprising: a color filter provided on a second surface side of the first substrate opposite the first surface side of the first substrate.
  7. 7 . The sensor device according to claim 1 , wherein the second substrate has a thickness of 10 μm or more and 200 μm or less.
  8. 8 . The sensor device according to claim 1 , wherein the second insulating film has a thickness of 10 μm or less.
  9. 9 . An electronic apparatus, comprising: an optical part; and a sensor device to receive, light that has been transmitted through the optical part, the sensor device including: a first substrate comprising an image sensor; a second substrate comprising a logic circuit for processing signals from the image sensor, the second substrate being provided on a first surface side of the first substrate; a first insulating film that is provided on the first surface side of the first substrate and that covers at least a side surface of the second substrate; and a second insulating film that is formed of a material different from that of the first insulating film and that is disposed in the first insulating film on a side of the first insulating film opposite the second substrate, wherein the second insulating film does not overlap second substrate in a plan view.
  10. 10 . The electronic apparatus according to claim 9 , wherein a surface of the second substrate and a surface of the second insulating film that are closest to one another are separated by part of the first insulating film.
  11. 11 . The electronic apparatus according to claim 9 , further comprising: a support substrate in contact with the first insulating film and the second insulating film.
  12. 12 . The electronic apparatus according to claim 9 , further comprising: a third substrate that is disposed on the side of the first surface side of the first substrate, wherein the first insulating film covers the third substrate, and wherein the second insulating film being does not overlap with the third substrate in the plan view.
  13. 13 . The electronic apparatus according to claim 9 , wherein the first substrate is part of a set of stacked substrates stacked in a thickness direction.
  14. 14 . The electronic apparatus according to claim 9 , further comprising: a color filter provided on a second surface side of the first substrate opposite the first surface side of the first substrate.
  15. 15 . The electronic apparatus according to claim 9 , wherein the second substrate has a thickness of 10 μm or more and 200 μm or less.
  16. 16 . The electronic apparatus according to claim 9 , wherein the second insulating film has a thickness of 10 μm or less.
  17. 17 . A vehicle control system, comprising: an electronic apparatus, comprising: an optical part; and a sensor device to receive light that has been transmitted through the optical part, the sensor device including: a first substrate comprising an image sensor; a second substrate comprising a logic circuit for processing signals from the image sensor, the second substrate being provided on a first surface side of the first substrate; a first insulating film that is provided on the first surface side of the first substrate and that covers at least a side surface of the second substrate; and a second insulating film that is formed of a material different from that of the first insulating film and that is disposed in the first insulating film on a side of the first insulating film opposite the second substrate, wherein the second insulating film does not overlap the second substrate in a plan view.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This application is a national stage application under 35 U.S.C. 371 and claims the benefit of PCT Application No. PCT/JP2021/029622, having an international filing date of 11 Aug. 2021, which designated the United States, which PCT application claimed the benefit of Japanese Patent Application No. 2020-141235, filed 24 Aug. 2020, the entire disclosures of each of which are incorporated herein by reference. TECHNICAL FIELD The present disclosure relates to a sensor device and an electronic apparatus. BACKGROUND ART A CoW (Chip on Wafer) in which a semiconductor chip is bonded to the surface of a wafer is known. For example, Patent Literature 1 discloses a method of producing an imaging device, which is a technology in which a logic chip including a logic circuit determined to be a non-defective product is bonded to the surface of a wafer, an insulating film is deposited on the surface of the wafer, and then the surface of the insulating film is flattened. CITATION LIST Patent Literature Patent Literature 1: WO 2019/087764Patent Literature 2: Japanese Patent Application Laid-open No. 2011-18710 DISCLOSURE OF INVENTION Technical Problem In the CoW, a step corresponding to the thickness of the semiconductor chip is generated between the semiconductor chip and the wafer surface. The thickness is approximately 10 μm to 200 μm even in the case where the semiconductor chip is thinned, so that the step described above is large. When an insulating film is deposited on the surface of the wafer so as to cover the semiconductor chip, recesses and projections reflecting the step between the semiconductor chip and the wafer surface are formed on the surface of the insulating film. In order to flatten the recesses and projections, CMP (Chemical Mechanical Polishing) processing is performed on the surface of the insulating film. However, the recesses and projections described above reflect the step between the semiconductor chip and the wafer surface, and the step is large, i.e., approximately 10 μm to 200 μm. For this reason, even in the case where CMP processing is performed, there is a possibility that the surface of the insulating film is not sufficiently flattened. For example, there is a possibility that a depression called a void or dishing occurs between a plurality of semiconductor chips bonded to the surface of the wafer or the outer periphery portion of the wafer. There is a possibility that poor bonding occurs between the insulating film and another substrate (e.g., support substrate) due to this depression. Further, stress is generated in the semiconductor chip due to the difference in coefficient of thermal expansion between the semiconductor chip and the insulating film. When this stress is large, there is a possibility that a load is applied to a transistor mounted on the semiconductor chip and the transistor characteristics (e.g., mobility) change. Further, when this stress is large, there is a possibility that positional deviation occurs between the semiconductor chip and a color filter provided on the insulating film covering the semiconductor chip. Regarding the semiconductor chip, there is a possibility that when the transistor characteristics change or positional deviation occurs between the semiconductor chip and the color filter, characteristics of the imaging device deteriorates. Note that Patent Literature 2 discloses a technology in which a conducive pattern is formed on a semiconductor substrate, a first polishing stop layer is formed on the conducive pattern, an interlayer insulating film is formed on the semiconductor substrate so as to cover the conducive pattern and the first polishing stop layer, a second polishing stop layer is formed on the interlayer insulating film, and then the first polishing stop layer and the interlayer insulating film located above the conducive pattern are polished to flatten the upper surface of the semiconductor substrate. However, the technology disclosed in Patent Literature 2 does not flatten a large step between a semiconductor chip and a wafer, which is generated in a CoW. The technology disclosed in Patent Literature 2 flattens a small step in a semiconductor chip, which is generated in a pre-process of a semiconductor process. The thickness of the conducive pattern (wiring layer) in the semiconductor chip is assumed to be less than 1 μm at maximum, which is much smaller than a step (approximately 10 μm to 200 μm) generated in a CoW. Patent Literature 2 does not describe improvement in the flatness of the insulating film covering the semiconductor chip and relaxation of stress generated in the semiconductor chip. The present disclosure has been made in view of such circumstances, and an object of the present disclosure is to provide a sensor device and an electronic apparatus that are capable of reducing the occurrence of defects. Solution to Problem A sensor device according to an aspect of the present disclosure in