US-12622082-B2 - Stacked CMOS image sensor with STI-free photodetector isolation and method for forming the same

Abstract

Various embodiments of the present disclosure are directed towards a stacked complementary metal-oxide semiconductor (CMOS) image sensor in which a pixel sensor spans multiple integrated circuit (IC) chips and is devoid of a shallow trench isolation (STI) structure at a photodetector of the pixel sensor. The photodetector and a first transistor form a first portion of the pixel sensor at a first IC chip. A plurality of second transistors forms a second portion of the pixel sensor at a second IC chip. By omitting the STI structure at the photodetector, a doped well surrounding and demarcating the pixel sensor may have a lesser width than it would otherwise have. Hence, the doped well may consume less area of the photodetector. This, in turn, allows enhanced scaling down of the pixel sensor.

Inventors

• Chi-Hsien Chung
• Tzu-Jui WANG
• Tzu-Hsuan Hsu
• Chen-Jong Wang
• Dun-Nian Yaung

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date

20260505

Application Date

20230105

Claims (20)

1. 1 . A method for forming an image sensor, comprising: forming a first integrated circuit (IC) chip, comprising: forming a pair of photodetectors bordering each other in a first substrate; doping the first substrate to form a shallow well and a deep well that share a doping type, wherein the shallow well extends into a first side of the first substrate, the deep well extends into a second side of the first substrate, opposite the first side, to the shallow well, and the shallow and deep wells are between and border the pair of photodetectors; and forming a pair of first transistors on the first side of the first substrate, adjacent respectively to the pair of photodetectors, wherein the pair of photodetectors and the pair of first transistors form a first pixel-sensor portion; forming a second IC chip, comprising: forming a plurality of second transistors on a second substrate, wherein the second transistors form a second pixel-sensor portion; and bonding the first and second IC chips together such that the first and second pixel-sensor portions are stacked and electrically coupled together to form a pixel sensor; wherein the first IC chip is devoid of a shallow trench isolation (STI) structure extending into the first side of the first substrate at the pair of photodetectors, and wherein the deep well has a width at the second side of the first substrate that corresponds to a separation between the pair of photodetectors.
2. 2 . The method according to claim 1 , wherein the shallow and deep wells surround and demarcate a photodetector region at which a photodetector of the pair of photodetectors and a transistor of the pair of first transistors are formed, wherein the first side of the first substrate is flat from a first sidewall of the first well to a second sidewall of the first well after forming the transistor, and wherein the first and second sidewalls respectively face and face away from the photodetector on a common side of the photodetector.
3. 3 . The method according to claim 1 , wherein the forming of the second IC chip comprises: patterning the second substrate to form a trench surrounding and demarcating device regions; and filling the trench with a dielectric material, wherein the second transistors are formed respectively on the device regions, such that the dielectric material separates and electrically isolates the second transistors from each other.
4. 4 . The method according to claim 1 , wherein a semiconductor surface of the first substrate, which is on the first side of the first substrate, extends continuously from a first photodetector of the pair of photodetectors to a second photodetector of the pair of photodetectors at an elevation level with a top of a source or drain region of a transistor of the pair of first transistors after the forming of the pair of first transistors.
5. 5 . The method according to claim 1 , further comprising: forming a third IC chip, comprising: forming a plurality of third transistors on a third substrate; and forming an interconnect structure covering the third transistors, wherein the third transistors and the interconnect structure form an application-specific integrated circuit (ASIC); and bonding the second and third IC chips together, such that the second IC chip is between the first and third IC chips and such that the ASIC is electrically coupled to the pixel sensor.
6. 6 . The method according to claim 1 , wherein the pair of first transistors share a common source/drain region formed atop the shallow well and having an opposite doping type as the shallow well.
7. 7 . The method according to claim 1 , wherein a photodetector of the pair of photodetectors comprises a doped collector region in the first substrate and having another doping type that is opposite the doping type of the shallow and deep wells, and wherein the doped collector region and the deep well have individual boundaries facing away from the first side of the first substrate and level with each other at the second side of the first substrate.
8. 8 . The method according to claim 1 , wherein the deep well has an additional width that is shared with the shallow well at an interface at which the shallow and deep wells contact each other, and wherein the additional width corresponds to the separation between the pair of photodetectors.
9. 9 . A method for forming an image sensor, comprising: forming a pair of photodetectors bordering in a first semiconductor substrate; forming a pair of first transistors respectively bordering the pair of photodetectors on a first surface of the first semiconductor substrate, wherein the pair of first transistors share a source or drain region in the first semiconductor substrate and the source or drain region overlies and is spaced from the pair of photodetectors; forming a plurality of second transistors on a second semiconductor substrate; and bonding the first and second semiconductor substrates together with the pair of first transistors being between the first and second semiconductor substrates; wherein the pair of photodetectors, the pair of first transistors, and the plurality of second transistors form a pixel sensor, and wherein the first surface of the first semiconductor substrate is level with a top of the source or drain region continuously from a first photodetector of the pair of photodetectors to a second photodetector of the pair of photodetectors.
10. 10 . The method according to claim 9 , wherein the pixel sensor has only one transistor per photodetector on the first semiconductor substrate.
11. 11 . The method according to claim 9 , wherein the pair of photodetectors comprise individual doped collector regions, which have a first doping type and which are formed in the first semiconductor substrate while forming the pair of photodetectors, and wherein the source or drain region is formed overlying and spaced from the individual doped collector regions and with the first doping type.
12. 12 . The method according to claim 11 , further comprising: forming a shallow well in the first semiconductor substrate, extending from the first surface of the first semiconductor substrate to a first depth; and forming a deep well in the first semiconductor substrate, extending from the shallow well at the first depth to a second surface of the first semiconductor substrate opposite the first surface, wherein the shallow well and the deep well laterally contact the individual doped collector regions of the pair of photodetectors and share a second doping type opposite the first doping type, and wherein the shallow well contacts the source or drain region.
13. 13 . The method according to claim 12 , further comprising: after the bonding, forming a deep trench isolation structure extending into the deep well from the second surface of the first semiconductor substrate, wherein the deep trench isolation structure is spaced from the shallow well.
14. 14 . The method according to claim 12 , wherein the shallow well and the deep well form an isolation region having a columnar profile between the pair of photodetectors and having a width that is substantially uniform from the source or drain region to the second surface of the first semiconductor substrate.
15. 15 . A method for forming an image sensor, comprising: forming a first photodetector and a second photodetector bordering in a first semiconductor substrate; forming a shallow well and a deep well between and bordering the first and second photodetectors, wherein the shallow well and the deep well are stacked with a common doping type and extend from a first side of the first semiconductor substrate to a second side of the first semiconductor substrate opposite the first side; forming a pair of first transistors respectively bordering the first and second photodetectors on the first side of the first semiconductor substrate, wherein the pair of first transistors share a common source/drain region on the shallow well; forming first bond pads overlying and electrically coupled to a first pixel-sensor portion formed by the first and second photodetectors and the pair of first transistors; forming a plurality of second transistors on a second semiconductor substrate; forming second bond pads overlying and electrically coupled to a second pixel-sensor portion formed by the plurality of second transistors; and bonding the second semiconductor substrate to the first semiconductor substrate via the first and second bond pads; wherein the bonding electrically couples the first and second pixel-sensor portions together to form a pixel sensor, and wherein the shallow well and the deep well share a common width at a periphery of the pixel sensor, and wherein the common source/drain region is spaced from the first and second photodetectors and fully separates the shallow well from the first side of the first semiconductor substrate in a cross-sectional plane.
16. 16 . The method according to claim 15 , wherein the shallow well, the deep well, and the common source/drain region have individual heights that sum to a height of the first semiconductor substrate.
17. 17 . The method according to claim 15 , wherein the common source/drain region has a width greater than the common width.
18. 18 . The method according to claim 15 , further comprising: forming a first interconnect structure overlying and electrically coupled to the pair of first transistors; forming a first bond structure overlying and electrically coupled to the first interconnect structure and comprising the first bond pads; forming a second interconnect structure overlying and electrically coupled to the plurality of second transistors; and forming a second bond structure overlying and electrically coupled to the second interconnect structure and comprising the second bond pads, wherein the first bond structure and the second bond structure contact during the bonding.
19. 19 . The method according to claim 15 , wherein the first photodetector comprises a doped collector region in the first semiconductor substrate and having a doping type opposite the common doping type, and wherein the doped collector region extends to the second side of the first semiconductor substrate and is spaced from the first side of the first semiconductor substrate.
20. 20 . The method according to claim 19 , wherein the first photodetector further comprises an additional doped collector region extending from the doped collector region towards the first side of the first semiconductor substrate, wherein the additional doped collector region has the doping type of the doped collector region and is spaced from the deep well, the shallow well, and the first side of the first semiconductor substrate, and wherein the doped collector region laterally contacts the shallow and deep wells.

Description

REFERENCE TO RELATED APPLICATION This application claims the benefit of U.S. Provisional Application No. 63/401,291, filed on Aug. 26, 2022, the contents of which are incorporated by reference in their entirety. BACKGROUND Integrated circuits (ICs) with image sensors are used in a wide range of modern-day electronic devices, such as, for example, cameras, cell phones, and the like. Types of image sensors include, for example, complementary metal-oxide semiconductor (CMOS) image sensors and charge-coupled device (CCD) image sensors. Compared to CCD image sensors, CMOS image sensors are increasingly favored due to low power consumption, small size, fast data processing, a direct output of data, and low manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 illustrates a schematic view of some embodiments of a stacked image sensor in which a first integrated circuit (IC) chip accommodates a photodetector and is devoid of shallow trench isolation (STI) structures at the photodetector. FIG. 2 illustrates another cross-sectional view of some embodiments of the first IC chip of FIG. 1. FIG. 3 illustrates a top layout view of some embodiments of the first IC chip of FIG. 1. FIGS. 4A-4F illustrate cross-sectional views of some alternative embodiments of the first IC chip of FIG. 1. FIG. 5 illustrates a cross-sectional view of some embodiments of a second IC chip of FIG. 1. FIG. 6 illustrates a top layout view of some embodiments of the second IC chip of FIG. 5. FIG. 7 illustrates a cross-sectional view of some embodiments of the stacked image sensor of FIG. 1 in which the second IC chip is illustrated by cross section. FIG. 8 illustrates a circuit diagram of some embodiments of the stacked image sensor of FIG. 1. FIG. 9 illustrates a circuit diagram of some alternative embodiments of the stacked image sensor of FIG. 1. FIG. 10 illustrates a schematic view of some alternative embodiments of the stacked image sensor of FIG. 1 in which a pixel sensor comprises a plurality of photodetectors and a plurality of first transistors. FIG. 11 illustrates a top layout view of some embodiments of the first IC chip of FIG. 10. FIG. 12 illustrates a cross-sectional view of some embodiments of the stacked image sensor of FIG. 10 in which a second IC chip is illustrated by cross section. FIG. 13 illustrates a circuit diagram of some embodiments of the stacked image sensor of FIG. 10. FIG. 14 illustrates a circuit diagram of some alternative embodiments of the stacked image sensor of FIG. 10. FIGS. 15A-15D illustrate block diagrams of some embodiments of a stacked image sensor in which the stacked image sensor comprises a trio of IC chips and in which an IC chip accommodating a photodetector is devoid of STI structures. FIGS. 16A and 16B illustrate block diagrams of some alternative embodiments of the stacked image sensor of FIGS. 15A-15D. FIG. 17 illustrates a top layout view of some embodiments of a first IC chip of the stacked image sensor of FIGS. 15A-15D. FIG. 18 illustrates a cross-sectional view of some embodiments of the stacked image sensor of FIGS. 15A-15D. FIG. 19 illustrates a circuit diagram of some embodiments of a pixel sensor of FIG. 18. FIG. 20 illustrates a circuit diagram of some alternative embodiments of a pixel sensor of FIG. 18. FIG. 21 illustrates a top layout view of some alternative embodiments of a first IC chip of the stacked image sensor of FIGS. 15A-15D. FIG. 22 illustrates a cross-sectional view of some alternative embodiments of the image sensor of FIGS. 15A-15D. FIG. 23 illustrates a circuit diagram of some embodiments of a pixel sensor of FIG. 22. FIG. 24 illustrates a circuit diagram of some alternative embodiments of a pixel sensor of FIG. 22. FIGS. 25-37 illustrate a series of cross-sectional views of some embodiments of a method for an image sensor devoid of STI structures at a first IC chip, which accommodates a photodetector of a pixel sensor. FIG. 38 illustrates a block diagram of some embodiments of the method of FIGS. 25-37. DETAILED DESCRIPTION The present disclosure provides many different embodiments, or examples, for implementing different features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between