US-12622084-B2 - Image sensor and image sensor manufacturing method

US12622084B2US 12622084 B2US12622084 B2US 12622084B2US-12622084-B2

Abstract

A multilayer wiring layer is laminated over a wafer. Wirings formed in the multilayer wiring layer include a capacitance control wiring and an FD-SF wiring. The capacitance control wiring is capacitively coupled with a floating diffusion, and a boost signal which increases a potential of the floating diffusion is transmitted on the capacitance control wiring. The FD-SF wiring connects the floating diffusion and a source follower transistor. The multilayer wiring layer includes an FD connection layer and a first control line layer. The FD-SF wiring is formed in the FD connection layer. The capacitance control wiring is formed in the first control line layer. In the multilayer wiring layer, the first control line layer is the wiring layer closest to the FD connection layer.

Inventors

Ikuko Inoue
Cynthia Sun Yee LEE

Assignees

OMNIVISION TECHNOLOGIES, INC.

Dates

Publication Date: 20260505
Application Date: 20240830
Priority Date: 20240401

Claims (20)

1 . An image sensor comprising: at least one wafer on which a photodiode which photoelectrically converts incident light, a floating diffusion which temporarily holds charges accumulated in the photodiode, and a source follower transistor which has a gate connected to the floating diffusion are formed; and a multilayer wiring layer laminated over the wafer, wherein wirings formed in the multilayer wiring layer includes: a capacitance control wiring which is capacitively coupled with the floating diffusion and on which a boost signal which increases a potential of the floating diffusion is transmitted; and an FD-SF wiring which connects the floating diffusion and the source follower transistor, the multilayer wiring layer include: an FD connection layer in which the FD-SF wiring is formed; and a first control line layer in which the capacitance control wiring is formed, and in the multilayer wiring layer, the first control line layer is a wiring layer which is closest to the FD connection layer.
2 . The image sensor according to claim 1 , wherein a transfer transistor which transfers charges photoelectrically converted by the photodiode to the floating diffusion is formed on the wafer, and in the first control line layer, a transfer wiring is formed on which a transfer signal for the transfer transistor is transmitted.
3 . The image sensor according to claim 2 , wherein a reset transistor which resets the potential of the floating diffusion to a reference potential is formed, the wirings formed in the multilayer wiring layer further include a reset wiring on which a reset signal for the reset transistor is transmitted, and the multilayer wiring layer further includes a second control line layer in which the reset wiring is formed.
4 . The image sensor according to claim 3 , wherein a row selection transistor which is connected to a source of the source follower transistor is formed, and in the second control line layer, a row selection wiring is formed on which a row selection signal for the row selection transistor is transmitted.
5 . The image sensor according to claim 4 , wherein the FD-SF wiring intersects the transfer wiring and the capacitance control wiring in a circuit plan view.
6 . The image sensor according to claim 5 , wherein the FD connection layer is formed in a first layer of the multilayer wiring layer, and the first control line layer is formed in a second layer of the multilayer wiring layer.
7 . The image sensor according to claim 6 , wherein in the multilayer wiring layer, the second control line layer is formed in a manner to be separated from the FD connection layer by three or more layers.
8 . The image sensor according to claim 7 , wherein the multilayer wiring layer further includes a constant voltage wiring layer in which a constant voltage wiring, including a reference potential wiring on which the reference potential is applied, is formed, and the constant voltage wiring layer is formed between the first control line layer and the second control line layer.
9 . The image sensor according to claim 3 , wherein the at least one wafer includes a pixel unit wafer, and a logic circuit unit wafer, the photodiode, the floating diffusion, and the transfer transistor are formed on the pixel unit wafer, the reset transistor, the row selection transistor, and the source follower transistor are formed on the logic circuit unit wafer, the FD connection layer is formed in a first layer of the multilayer wiring layer of the pixel unit wafer, the first control line layer is formed in a second layer of the multilayer wiring layer of the pixel unit wafer, the second control line layer is formed in the multilayer wiring layer of the logic circuit unit wafer, and the multilayer wiring layer of the logic circuit unit wafer is laminated in an opposing manner over the multilayer wiring layer of the pixel unit wafer.
10 . The image sensor according to claim 9 , wherein the multilayer wiring layer further includes a constant voltage wiring layer in which a constant voltage wiring, including a reference potential wiring on which the reference potential is applied, is formed, the second control line layer is formed in a first layer of the multilayer wiring layer of the logic circuit unit wafer, the constant voltage wiring layer is formed in a second layer of the multilayer wiring layer of the logic circuit unit wafer, and the constant voltage wiring layer on the logic circuit unit wafer is laminated over the first control line layer on the pixel unit wafer.
11 . The image sensor according to claim 3 , wherein the at least one wafer includes a pixel unit wafer and a logic circuit unit wafer, the photodiode, the floating diffusion, the source follower transistor, and the transfer transistor are formed on the pixel unit wafer, the reset transistor and the row selection transistor are formed on the logic circuit unit wafer, the FD connection layer is formed in a first layer of the multilayer wiring layer of the pixel unit wafer, the first control line layer is formed in a second layer of the multilayer wiring layer of the pixel unit wafer, the second control line layer is formed in the multilayer wiring layer of the logic circuit unit wafer, and the multilayer wiring layer of the logic circuit unit wafer is laminated in an opposing manner over the multilayer wiring layer of the pixel unit wafer.
12 . The image sensor according to claim 3 , wherein an additional capacitance and a selective conversion gain transistor provided between the additional capacitance and the floating diffusion are formed on the wafer, the wirings formed in the multilayer wiring layer further include a selective conversion gain transistor wiring on which a connection signal for the selective conversion gain transistor is transmitted, and the selective conversion gain transistor wiring is formed in the second control line layer.
13 . An image sensor comprising: at least one wafer on which a photodiode which photoelectrically converts incident light, a transfer transistor which transfers charges photoelectrically converted by the photodiode, a floating diffusion which temporarily holds charges transferred from the transfer transistor, a reset transistor which resets a potential of the floating diffusion to a reference potential, and a source follower transistor which has a gate connected for the floating diffusion are formed; and a multilayer wiring layer laminated over the wafer, wherein wirings formed in the multilayer wiring layer include: a transfer wiring on which a transfer signal for the transfer transistor is transmitted; a capacitance control wiring which is capacitively coupled with the floating diffusion and on which a boost signal which increases the potential of the floating diffusion is transmitted; a reset wiring on which a reset signal for the reset transistor is transmitted; and an FD-SF wiring which connects the floating diffusion and the source follower transistor, in the multilayer wiring layer, the transfer wiring, the capacitance control wiring, and the reset wiring are formed in a single layer, and the transfer wiring and the capacitance control wiring have wider wiring widths than the reset wiring.
14 . The image sensor according to claim 13 , wherein a row selection transistor which is connected to a source of the source follower transistor is formed on the wafer, the wirings formed in the multilayer wiring layer further include a row selection wiring on which a row selection signal for the row selection transistor is transmitted, in the multilayer wiring layer, in addition to the transfer wiring, the capacitance control wiring, and the reset wiring, the row selection wiring is formed in the single layer, and the row selection wiring has a narrower wiring width than the transfer wiring and the capacitance control wiring.
15 . A method of manufacturing an image sensor, comprising: forming, on at least one wafer, a photodiode which photoelectrically converts incident light, a floating diffusion which temporarily holds charges accumulated in the photodiode, and a source follower transistor which has a gate connected to the floating diffusion; laminating a multilayer wiring layer over the wafer, wherein wirings included in the multilayer wiring layer include a capacitance control wiring which is capacitively coupled with the floating diffusion, and on which a boost signal which increases a potential of the floating diffusion is transmitted, and an FD-SF wiring which connects the floating diffusion and the source follower transistor; forming, as the multilayer wiring layer, an FD connection layer in which the FD-SF wiring is formed, and a first control line layer in which the capacitance control wiring is formed; and placing the first control line layer closest to the FD connection layer among the wiring layers of the multilayer wiring layer.
16 . The method of manufacturing the image sensor according to claim 15 , further comprising: forming, on the wafer, a transfer transistor which transfers charges photoelectrically converted by the photodiode to the floating diffusion; and forming, in the first control line layer, a transfer wiring on which a transfer signal for the transfer transistor is transmitted.
17 . The method of manufacturing the image sensor according to claim 16 , further comprising: forming a reset transistor which resets the potential of the floating diffusion to a reference potential, wherein the wirings formed in the multilayer wiring layer further include a reset wiring on which a reset signal for the reset transistor is transmitted; and forming, as the multilayer wiring layer, a second control line layer in which the reset wiring is formed.
18 . The method of manufacturing the image sensor according to claim 17 , further comprising: forming a row selection transistor which is connected to a source of the source follower transistor; and forming a row selection wiring, on which a row selection signal for the row selection transistor is transmitted, in the second control line layer.
19 . The method of manufacturing the image sensor according to claim 17 , wherein the at least one wafer includes a pixel unit wafer and a logic circuit unit wafer, and the method further comprises: forming the photodiode, the floating diffusion, and the transfer transistor on the pixel unit wafer; forming the reset transistor and the source follower transistor on the logic circuit unit wafer; forming the FD connection layer in a first layer of the multilayer wiring layer of the pixel unit wafer; forming the first control line layer in a second layer of the multilayer wiring layer of the pixel unit wafer; forming the second control line layer in the multilayer wiring layer of the logic circuit unit wafer; and laminating the multilayer wiring layer of the logic circuit unit wafer in an opposing manner over the multilayer wiring layer of the pixel unit wafer.
20 . A method of manufacturing an image sensor, comprising: forming, on at least one wafer, a photodiode which photoelectrically converts incident light, a transfer transistor which transfers charges photoelectrically converted by the photodiode, a floating diffusion which temporarily holds charges transferred from the transfer transistor, a reset transistor which resets a potential of the floating diffusion to a reference potential, and a source follower transistor which has a gate connected to the floating diffusion; laminating a multilayer wiring layer over the wafer, wherein wirings formed in the multilayer wiring layer include a transfer wiring on which a transfer signal for the transfer transistor is transmitted, a capacitance control wiring which is capacitively coupled with the floating diffusion and on which a boost signal which increases the potential of the floating diffusion is transmitted, a reset wiring on which a reset signal for the reset transistor is transmitted, and an FD-SF wiring which connects the floating diffusion and the source follower transistor; forming the transfer wiring, the capacitance control wiring, and the reset wiring in a single layer in the multilayer wiring layer; and forming the transfer wiring and the capacitance control wiring with wider wiring widths than the reset wiring.

Description

CROSS REFERENCE TO RELATED APPLICATION This application claims priority to Japanese Patent Application No. 2024-058752 filed on Apr. 1, 2024, which is incorporated herein by reference in its entirety including the specification, claims, drawings, and abstract. TECHNICAL FIELD The present specification discloses an image sensor and its manufacturing method. BACKGROUND For example, US 2023/0179883 A discloses a photoelectric conversion apparatus. Charges accumulated in a photoelectric conversion unit (photodiode) are transferred to a floating diffusion unit by a transfer transistor. The photoelectric conversion apparatus comprises a wiring layer. In the wiring layer, a transfer control line, a connection wiring, and a shield wiring are provided. A drive signal for the transfer transistor is transmitted to the transfer control line. The connection wiring connects the floating diffusion unit and a gate of an amplification transistor. Further, the shield wiring is provided between the connection wiring and the transfer control line. Charges accumulated in the photodiode are transferred to the floating diffusion. As a value showing detection efficiency of the charges, a conversion gain is used. The conversion gain indicates a signal voltage [μV] or a digital value (DN) obtained per one electron of the signal. If a large signal voltage or a large digital value is obtained with a small number of electrons, the conversion gain is high. As such, as a capacitance of the floating diffusion becomes smaller, the conversion gain becomes higher. The floating diffusion may be likened to a well which stores charges. In the floating diffusion, in order to increase the conversion gain, the capacitance must be reduced to increase a potential. When the potential is small, phenomena such as “lag” in which charges remain in the photodiode, or “injection” in which charges are injected from the floating diffusion to the photodiode are more likely to occur. In addition, a “feedthrough” may occur, in which, when a pulse signal is applied to a terminal in an image sensor, a potential of another terminal is varied through a parasitic capacitance. When the potential of the floating diffusion is reduced (i.e., when the well is shallowed) due to the feedthrough, the lag and the injection are even more likely to occur. In view of the above, the present specification discloses an image sensor capable of suppressing lag and injection while suppressing feedthrough that reduces the potential of the floating diffusion, and a manufacturing method thereof. SUMMARY An image sensor disclosed herein includes at least one wafer, and a multilayer wiring layer. On the wafer, a photodiode, a floating diffusion FD, and a source follower transistor SF are formed. The photodiode photoelectrically converts incident light. The floating diffusion temporarily holds charges accumulated in the photodiode. The source follower transistor has a gate connected to the floating diffusion. The multilayer wiring layer is laminated over the wafer. Wirings formed in the multilayer wiring layer include a capacitance control wiring and an FD-SF wiring. The capacitance control wiring is capacitively coupled with the floating diffusion, and a boost signal which increases a potential of the floating diffusion is transmitted thereon. The FD-SF wiring connects the floating diffusion and the source follower transistor. The multilayer wiring layer includes an FD connection layer and a first control line layer. The FD-SF wiring is formed in the FD connection layer. The capacitance control wiring is formed in the first control line layer. In the multilayer wiring layer, the first control line layer is a wiring layer which is closest to the FD connection layer. According to the above configuration, the FD-SF wiring and the capacitance control wiring are placed close to each other. Accordingly, a large-capacitance wiring capacitance is caused between the FD-SF wiring and the capacitance control wiring. In the process of transferring the charges stored in the photodiode to the floating diffusion, when the boost signal is transmitted on the capacitance control wiring, the potential of the floating diffusion is sufficiently increased (i.e., the well is deepened). In addition, with the configuration in which the first control line layer is the closest to the FD connection layer, the wiring layer which would reduce the potential of the floating diffusion can be separated from the FD connection layer. In other words, because a wiring pitch is widened, the wiring capacitance can consequently be reduced. In the above configuration, a transfer transistor may be formed. The transfer transistor transfers charges photoelectrically converted by the photodiode to the floating diffusion. In this configuration, a transfer wiring is formed in the first control line layer. On the transfer wiring, a transfer signal for the transfer transistor is transmitted. As shown, at a time t4 in FIG. 2 to be describ