US-12622121-B2 - Monolithic LED array and a precursor thereto

US12622121B2US 12622121 B2US12622121 B2US 12622121B2US-12622121-B2

Abstract

A monolithic LED array precursor comprising a plurality of LED structures sharing a first semiconductor layer, wherein the first semiconductor layer defines a plane of the LED array precursor, each LED structure comprising (i) a second semiconductor layer on the first semiconductor layer, having an upper surface portion parallel to the plane of the LED array precursor, the second semiconductor layer having a regular trapezoidal cross-section normal to the upper surface portion, such that the second semiconductor layer has sloped sides, (ii) a third semiconductor layer on the second semiconductor layer, having an upper surface portion parallel to the plane of the LED array precursor, the third semiconductor layer having a regular trapezoidal cross-section normal to the upper surface portion, such that the third semiconductor layer has sloped sides parallel to the sloped sides of the second semiconductor layer, (iii) a fourth semiconductor layer on the third semiconductor layer, having an upper surface portion parallel to the plane of the LED array precursor, the fourth semiconductor layer having a regular trapezoidal cross-section normal to the upper surface portion, such that the fourth semiconductor layer has sloped sides parallel to the sloped sides of the third semiconductor layer, (iv) a primary electrical contact on the fourth semiconductor layer, wherein the contact is only on the upper surface portion of the fourth semiconductor layer which is parallel to the plane of the LED array precursor, (v) electrically insulating, optically transparent spacers on the sloped sides of the fourth semiconductor layer, the spacers having an internal surface facing the sloped sides of the fourth semiconductor layer and an opposing external surface and (vi) a reflecting layer, electrically conducting extending over the external surface of the spacers, wherein the third semiconductor layer comprises a plurality of quantum well sub-layers, the quantum well sub-layers having a greater thickness on a portion parallel to the plane of the LED array precursor and a reduced thickness on a portion which is not parallel to the plane of the LED array precursor.

Inventors

Andrea Pinos
Samir Mezouari
WeiSin TAN
John Lyle WHITEMAN

Assignees

PLESSEY SEMICONDUCTORS LTD

Dates

Publication Date: 20260505
Application Date: 20210528
Priority Date: 20200603

Claims (8)

1 . A method of forming a monolithic LED array precursor, the method comprising: (i) providing a substrate having a surface; (ii) forming a continuous first semiconductor layer on the surface of the substrate; (iii) selectively masking the first semiconductor layer, by depositing a masking layer, which comprises a plurality of apertures, on the first semiconductor layer; (iv) growing a second semiconductor layer on unmasked portions of the first semiconductor layer, through the apertures of the masking layer to form a plurality of columns each having a regular trapezoidal cross-section normal to the substrate with sloped sides and a substantially flat upper surface portion; (v) forming a third semiconductor layer covering the second semiconductor layer, wherein the third semiconductor layer comprises one or more quantum well sub-layers and has sloped sides and a substantially flat upper surface portion; (vi) forming a fourth semiconductor layer covering the third semiconductor layer, whereby the fourth semiconductor layer has sloped sides and a substantially flat upper surface portion; (vii) forming primary electrical contacts on the substantially flat upper surface portion of the fourth semiconductor layer; and wherein the first to fourth semiconductor layers comprise Group III-nitrides; (viii) forming optically transparent spacers comprising electrically insulating material on the sloped sides of the fourth semiconductor layer, the spacers having an internal surface facing the sloped sides of the fourth semiconductor layer and an opposing external surface, wherein the external surface of the spacers has a parabolic profile; and (ix) depositing a reflecting, electrically conducting layer over the external surface of the spacers.
2 . The method according to claim 1 , wherein step (iii) comprises: (a) depositing a continuous masking layer, and (b) selectively removing a plurality of portions of said mask layer to provide a plurality of apertures.
3 . A method according to claim 1 , wherein forming the primary electrical contacts comprises depositing a transparent conducting oxide having an internal surface in contact with the substantial flat upper surface portion of the fourth semiconductor layer, and wherein the transparent conducting oxide has a convex external surface.
4 . A method according to claim 3 further comprising depositing a reflective, electrically conducting layer over the convex external surface of the transparent conducting oxide.
5 . A method according to claim 1 , wherein the spacers comprise a transparent conducting oxide and an insulating layer is provided between the transparent conducting oxide spacers and the underlying first semiconductor layer and/or wherein the spacers are formed of any one of silicon dioxide, silicon nitride or titanium oxide.
6 . A method according to claim 1 , wherein the internal surface of the spacers is formed of a first material and the external surface of the spacers is formed of a second material, and wherein the first material has a higher index of refraction than the second material.
7 . A method according to claim 1 , the method further comprising forming one or more secondary electrical contacts in electrical communication with the primary electrical contacts across the quantum well sublayers to form a monolithic LED array.
8 . A method according to claim 1 , further comprising a step of at least partially removing the substrate, and at least partially removing the first semiconductor layer to form a plurality of dome or lens structures corresponding to and aligned with each of the plurality of columns of the second semiconductor layer.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a 35 U.S.C. § 371 national stage application of PCT International Application No. PCT/GB2021/051331, filed on May 28, 2021, which claims the benefit of Great Britain Application No. 2008338.2, filed Jun. 3, 2020, which are hereby incorporated by reference in their entirety. FIELD OF THE INVENTION The present disclosure relates to a monolithic LED array, an LED device comprising the monolithic LED array and a method of manufacture thereof. In particular, the present disclosure provides a monolithic LED array having improved light emission. BACKGROUND OF THE INVENTION Micro light emitting diode (LED) arrays may be defined as arrays of LEDs with a size of 100×100 μm2 or less. Micro LED arrays are being developed for a number of commercial as well as military applications, such as self-emitting micro-displays and projectors, which may be incorporated into a variety of devices such as wearable displays, head-up displays, camcorders, viewfinders, multisite excitation sources, and pico-projectors. Group III-nitride-based micro LEDs are inorganic semiconductor LEDs containing GaN and its alloys with InN and AlN in the active light-emitting region. Group III-nitride based micro LEDs are popular as they can be driven at significantly higher current density and emit a higher optical power density than conventional large area LEDs, especially organic light emitting diode (OLED) in which the light-emitting layer is an organic compound. As a result, higher luminance (brightness), defined as the amount of light emitted per unit area of the light source in a given direction, also measured in candela per square meter (cd/m2) and commonly referred to as a Nit (nt), makes micro LEDs suitable for applications requiring, or benefiting from, high brightness, e.g., displays in high brightness environments or projection. Additionally, high luminous efficacy expressed in lumens per watt (lm/W) in group III-nitride micro LEDs, allows lower power usage compared with other light sources and makes micro LEDs particularly suitable for portable devices. Furthermore, owing to the intrinsic material properties of group III-nitrides, micro LEDs can be operated at extreme conditions such as high or low temperatures and humidity thereby providing a performance and reliability advantage in wearable and outdoor applications. Two main approaches currently exist for the production of inorganic micro LED arrays. In the first approach, individual micro LED devices are produced with techniques similar to those for conventional sized LEDs, these are then assembled as an array by pick and place technique onto a substrate, which may be an active matrix backplane which includes the driving circuitry for individual micro LED addressing. This first approach allows LEDs with different properties, such as different emission wavelengths, that have been fabricated on different growth substrates to be transferred onto the product substrate for the purpose of achieving full colour displays. Additionally, it allows discarding faulty devices before they become part of an array potentially improving the final yield of the array. On the other hand, the resolution (small pitch) and array size (large number of micro LEDs) that are required in a variety of applications pose severe challenges to this approach in terms of pick and place accuracy and transfer time, affecting the reliability of the process and its throughput, respectively. The second approach uses monolithic integration to fabricate the micro LED array on a single growth substrate, thus allowing a higher integration density, smaller LEDs and smaller pitch (i.e. higher array resolution). This second approach relies on colourisation techniques to achieve full colour displays. The colourisation technology used for micro LEDs depends on the micro LED array pitch. Conventional phosphor materials for lighting applications are currently only suitable for large pitch and low resolution arrays, and quantum dot-based wavelength converting materials are required for higher resolution applications. Regardless of the used approach, the perimeter of the active region of individual micro LEDs within an array is generally formed by an etching process that removes a portion of the light-emitting active region, thereby electrically isolating individual micro LEDs for the purpose of allowing independent current injection in each micro LED and tuning of the amount of radiative recombination within each micro LED in the array. A less commonly employed manufacturing process uses selective area growth (SAG) to achieve an electrically isolated portion of active region that can be independently injected with a current without using an etching step as disclosed in U.S. Pat. No. 7,087,932. In the selective area growth technique, a mask is patterned on a buffer layer. The material in the mask is such that at the growth conditions, no additional material is grown directly on