US-12622123-B2 - Method for manufacturing an optoelectronic device

US12622123B2US 12622123 B2US12622123 B2US 12622123B2US-12622123-B2

Abstract

A method for manufacturing an optoelectronic device includes providing a support supporting a plurality of three-dimensional semiconductor structures, forming a sacrificial portion under a first set of 3D structures of the plurality of three-dimensional semiconductor structures, forming a barrier portion around the sacrificial portion, said barrier portion having a basal wall extending under the sacrificial portion, and a lateral wall extending at the edge of the sacrificial portion, forming an access trench up to the sacrificial portion, the access trench extending continuously along the lateral wall of the barrier portion, etching the sacrificial portion from the access trench, and removing the first set of 3D structures.

Inventors

Xavier Hugon
Eric Pourquier
Frédéric MAYER
Thomas Lacave
Philippe Gibert
Mickaël REBAUD
Emmanuel Petitprez

Assignees

Aledia

Dates

Publication Date: 20260505
Application Date: 20210810
Priority Date: 20200831

Claims (17)

1 . A method of manufacturing an optoelectronic device comprising at least one first area devoid of three-dimensional semiconductor structures and at least one second area provided with three-dimensional 3D semiconductor structures, said method comprising: providing a support that supports a plurality of three-dimensional semiconductor structures on a basal plane xy, said structures each having a base turned towards a first side and an apex opposite the base, turned away from the first side and turned towards a second side opposite the first side, the first side being the real face of the device, and the second side being the front face of the device, forming, from the first side, a sacrificial portion under the bases of a first set of 3D structures of the plurality of three-dimensional semiconductor structures, forming a barrier portion around the sacrificial portion, said barrier portion having a basal wall extending under the sacrificial portion, and a lateral wall extending at the edge of the sacrificial portion, said lateral wall separating, in projection in a direction z normal to the basal plane xy, the first set of 3D structures from a second set of 3D structures of the plurality of three-dimensional semiconductor structures, forming, from the second side, an access trench up to the sacrificial portion, said access trench extending continuously along the lateral wall of the barrier portion, in projection in the direction z normal to the basal plane, etching the sacrificial portion from the access trench, and removing the first set of 3D structures, so as to define the at least one first area of the device.
2 . The method according to claim 1 , wherein etching the sacrificial portion has an etching selectivity S 30:50 of the material of the sacrificial portion in relation to the material of the barrier portion greater than or equal to 5:1.
3 . The method according to claim 1 , wherein the formation of the access trench is carried out by anisotropic etching mainly directed in the direction z normal to the basal plane xy and wherein the etching of the sacrificial portion is an isotropic etching.
4 . The method according to claim 1 , wherein the access trench is formed between the structures of the first set and the lateral wall of the barrier portion, in projection in the direction z normal to the basal plane xy.
5 . The method according to claim 1 , further comprising, before forming the access trench, forming a contact area under the bases of the first set of 3D structures, said contact area being intended to contact a driving electronics of the device.
6 . The method according to claim 5 , further comprising, before forming the access trench, assembling a driving electronics of the device at the contact area.
7 . The method according to claim 1 , wherein the sacrificial portion is made of a metal material and the barrier portion is made of a dielectric material.
8 . The method according to claim 7 , comprising: depositing from the first side a first metal layer corresponding to a first level, then etching said first metal layer from the first side, configured to define the sacrificial portion in the first metal layer, and depositing from the first side a dielectric layer, configured to encapsulate the sacrificial portion and form the barrier portion.
9 . The method according to claim 6 , further comprising: depositing from the first side a first metal layer corresponding to a first level, then etching said first metal layer from the first side, configured to define the sacrificial portion in the first metal layer, depositing from the first side a dielectric layer, configured to encapsulate the sacrificial portion and form the barrier portion, before assembling the driving electronics, depositing from the first side a second metal layer corresponding to a second level, on the dielectric layer, then etching said second metal layer from the first side, configured to define the contact area in the second metal layer, and after assembling the driving electronics and removing the first set of 3D structures, etching the dielectric barrier portion, from the second side, configured to expose a face of the contact area thus defined, facing the second side and wherein the sacrificial portion is made of a metal material and the barrier portion is made of a dielectric material.
10 . The method according to claim 1 , wherein the sacrificial portion is made of a dielectric material and the barrier portion is made of a metal material.
11 . The method according to claim 10 , comprising: depositing from the first side a dielectric layer, in such a way that a portion of said dielectric layer located under the first set of 3D structures forms the sacrificial portion, etching the dielectric layer at the edge of the first set of 3D structures, in projection in a direction z normal to the basal plane xy, followed by a metal deposition, configured to form the lateral wall of the barrier portion, depositing from the first side a second metal layer corresponding to a second level, on the portion of the dielectric layer forming the sacrificial portion and flush with the lateral wall, etching said second metal layer from the first side, configured to define the basal portion of the barrier portion in the second metal layer and in contact with the lateral wall.
12 . The method according to claim 11 , wherein the contact area is formed directly by the basal wall of the barrier portion and further comprising: before forming the access trench, forming a contact area under the bases of the first set of 3D structures, said contact area being intended to contact a driving electronics of the device.
13 . The method according to claim 11 , wherein the portion of the dielectric layer forming the sacrificial portion is structured before depositing the second metal layer, so as to form alignment marks protruding from the basal wall of the barrier portion, said alignment marks making it possible for example to facilitate a subsequent formation of a colour converter module.
14 . The method according to claim 1 , further comprising forming a colour converter module at the structures of the second set.
15 . The method according to claim 14 , wherein the formation of the colour converter module is carried out before removing the first set of 3D structures.
16 . The method according to claim 14 , wherein the formation of the colour converter module is carried out after removing the first set of 3D structures.
17 . The method according to claim 16 , wherein the contact area is protected by a protective layer during the formation of the colour converter module and further comprising: before forming the access trench, forming a contact area under the bases of the first set of 3D structures, said contact area being intended to contact a driving electronics of the device.

Description

TECHNICAL FIELD OF THE INVENTION The invention relates to the field of semiconductor technologies. It is particularly advantageously applicable in the manufacture of optoelectronic devices comprising three-dimensional structures, for example light-emitting diodes based on semiconductor wires or nanowires. PRIOR ART The so-called 3D architectures of microelectronic and optoelectronic devices based on arrays of three-dimensional semiconductor structures, such as nanowires or microwires, are considered as promising alternatives to conventional architectures based on two-dimensional semiconductor structures, such as flat layers. Such devices with 3D architecture may have an improved overall efficiency. Ordered arrays of nanowires based on a semiconductor material such as GaN, or more generally based on a direct gap material for optoelectronics, often have a crystalline quality higher than that of a flat layer based on the same material. This makes it possible for example to improve the emission of light from an optoelectronic device such as a light-emitting diode with 3D architecture (3D LED). The optical properties of such arrays also make it possible to improve the extraction of the light. The manufacture of functional optoelectronic devices with 3D architecture requires structuring the ordered arrays of 3D structures, particularly to define contact areas of the device. These ordered arrays of 3D structures may also be connected to a driving electronics. Generally, the driving electronics of a 3D LED is attached to a rear face of the nanowire array or arrays. It is then necessary to create an access area or an opening through the nanowire array to clear a contact area of the driving electronics, usually called “pad” or “CMOS pad” for a driving electronics based on CMOS transistors (Complementary Metal-Oxide-Semiconductor). A plurality of known solutions make it possible to form an area devoid of 3D structures. Thus, one solution consists of locally growing the array of 3D structures at emission areas of the 3D LED, by masking the areas where the 3D structures are undesirable, typically the contact areas intended to contact the driving electronics of the device. Such a solution often results in an inhomogeneity and/or discontinuities in the array of 3D structures, generally due to disturbances of the growth at the edges of the masked areas. This affects the performances of 3D optoelectronic devices. Another solution disclosed in the document EP 2936571 A1 consists of growing the 3D structures homogeneously on the entire surface of the wafer, then removing them from the areas where these are undesirable. The removal of 3D structures may be carried out by localised etching or via a mechanical action for example. This generally induces roughness problems that are detrimental in the method for manufacturing 3D LED. The reproducibility of the method is degraded. The present invention aims to overcome at least partially the abovementioned drawbacks. In particular, one object of the present invention is to propose a method for manufacturing a 3D optoelectronic device having an improved reproducibility. Another object of the invention is to propose a method for manufacturing a 3D optoelectronic device making it possible to clear a contact area intended to contact a driving electronics of the device. The other aims, features and advantages of the present invention will appear upon examination of the following description and accompanying drawings. It is understood that other advantages may be incorporated. SUMMARY OF THE INVENTION To achieve the abovementioned objectives, a first aspect of the invention relates to a method for manufacturing an optoelectronic device comprising at least one first area devoid of three-dimensional (3D) semiconductor structures and at least one second area provided with three-dimensional (3D) semiconductor structures. This method comprises the following steps: Providing a support supporting on a basal plane a plurality of three-dimensional semiconductor structures, said structures each having a base turned towards a first side, also called rear face, and an apex opposite the base, turned towards a second side, also called front face, opposite the first side,Forming, from the first side, a sacrificial portion under the bases of a first set of 3D structures of the plurality of three-dimensional semiconductor structures,Forming a barrier portion around the sacrificial portion, said barrier portion having a basal wall extending under the sacrificial portion, and a lateral wall extending at the edge of the sacrificial portion, said lateral wall separating, in projection in a direction normal to the basal plane, the first set of 3D structures of a second set of 3D structures of the plurality of three-dimensional semiconductor structures,Forming, from the second side, an access trench up to the sacrificial portion, said access trench extending continuously along the lateral wall of the barrier por