US-12622124-B2 - Multi-level device and method of manufacturing the same

US12622124B2US 12622124 B2US12622124 B2US 12622124B2US-12622124-B2

Abstract

Disclosed herein are a multi-level device which has a ternary characteristic and can reduce hysteresis, and a method of manufacturing the same. The multi-level device can have a plurality of turn-on voltages, that is, a plurality of threshold voltages, thereby providing multi-level conductivity as a ternary device characteristic. In addition, a double insulating layer made of a dielectric layer and an organic polymer layer is used as a separation layer for channel layer separation, and by removing the hysteresis due to a trap charge at an interface between a channel layer and an insulating layer, a uniform ternary characteristic can always be maintained, and by forming the channel layer on an organic polymer layer, the channel layer can be more stably formed on the insulating layer.

Inventors

Byoung Hun Lee
Yong Su LEE

Assignees

POSTECH Research and Business Development Foundation

Dates

Publication Date: 20260505
Application Date: 20230127
Priority Date: 20220627

Claims (11)

1 . A multi-level device comprising: a substrate; a gate electrode formed on the substrate; a first separation layer formed on the substrate and the gate electrode; a first channel layer formed on the first separation layer; a second separation layer formed on the first channel layer; a second channel layer formed on the second separation layer; and a source electrode and a drain electrode which are formed on the second channel layer, wherein each of the first separation layer and the second separation layer includes an organic polymer layer, wherein the first separation layer includes: a first dielectric layer formed on the substrate and the gate electrode; and a first organic polymer layer formed on the first dielectric layer, and wherein the second separation layer includes: a second dielectric layer formed on the first channel layer; and a second organic polymer layer formed on the second dielectric layer.
2 . The multi-level device of claim 1 , wherein the first dielectric layer and the second dielectric layer are each formed of any one material among aluminum oxide, aluminum nitride, aluminum oxynitride, and aluminum nitride oxide.
3 . The multi-level device of claim 1 , wherein each of the first organic polymer layer and the second organic polymer layer includes a polymer-based material.
4 . The multi-level device of claim 3 , wherein the polymer-based material includes any one material of polymethyl methacrylate (PMMA) and polystyrene (PS).
5 . The multi-level device of claim 1 , wherein: the first separation layer has a thickness ranging from 30 nm to 50 nm; and the first organic polymer layer has a thickness that is greater than a thickness of the first dielectric layer.
6 . The multi-level device of claim 1 , wherein: the second separation layer has a thickness ranging from 30 nm to 50 nm; and the second organic polymer layer has a thickness that is greater than a thickness of the second dielectric layer.
7 . The multi-level device of claim 1 , wherein each of the first organic polymer layer and the second organic polymer layer has a thickness ranging from 20 nm to 30 nm.
8 . The multi-level device of claim 1 , wherein a gate voltage applied to the gate electrode is in a first voltage range, a second voltage range, and a third voltage range as the gate voltage increases in a negative direction according to an operation of the first channel layer or the second channel layer.
9 . The multi-level device of claim 8 , wherein: a channel is formed in the second channel layer in the first voltage range; and the channel of the second channel layer is maintained in the third voltage range, and a channel is formed in the first channel layer.
10 . The multi-level device of claim 8 , wherein: a channel is formed in the second channel layer in the first voltage range; and a current flowing in the second channel layer is saturated in the second voltage range.
11 . The multi-level device of claim 8 , wherein a threshold voltage for forming a channel in the first voltage range and a threshold voltage for forming a channel in the third voltage range have different values.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to Korean Patent Application No. 10-2022-0078412 filed on Jun. 27, 2022 in the Korean Intellectual Property Office (KIPO), the entire contents of which are hereby incorporated by reference. BACKGROUND 1. Technical Field The present invention is related to a multi-level device and a method of manufacturing the same, and more particularly, to a multi-level device having a ternary characteristic and a method of manufacturing the same. 2. Related Art While the demand for low-power and high-integration devices is increasing due to the recent development of the digital information communication and home appliance industries, it is known that the power consumption and high integration of devices based on conventional charge control have reached a limit. Meanwhile, multi-level devices (multi-valued logics) are being researched to replace logic devices (logic architectures), and research on ternary logic devices using three logic states is being actively conducted. Since a multi-level device can reduce the number of transistors and a length of an interconnection connecting devices when compared to a binary logic device, it is expected to be able to greatly reduce power consumption. However, the multi-level device has a problem in that, when a voltage of a specific level is applied to a gate electrode, a current value between a source electrode and a drain electrode is not always maintained uniformly due to a hysteresis characteristic. RELATED ART DOCUMENT Patent Document (Patent Document 1) Korean Patent Laid-Open Application No. 10-2008-0083126 SUMMARY The present invention provides a multi-level device having a ternary characteristic and capable of reducing hysteresis, and a method of manufacturing the same. In some example embodiments, a multi-level device includes a substrate, a gate electrode formed on the substrate, a first separation layer formed on the substrate and the gate electrode, a first channel layer formed on the first separation layer, a second separation layer formed on the first channel layer, a second channel layer formed on the second separation layer, and a source electrode and a drain electrode which are formed on the second channel layer, wherein each of the first separation layer and the second separation layer includes an organic polymer layer. The first separation layer may include a first dielectric layer formed on the substrate and the gate electrode, and a first organic polymer layer formed on the first dielectric layer. The second separation layer may include a second dielectric layer formed on the first channel layer, and a second organic polymer layer formed on the second dielectric layer. The first dielectric layer and the second dielectric layer may each be formed of any one material among aluminum oxide, aluminum nitride, aluminum oxynitride, and aluminum nitride oxide. Each of the first organic polymer layer and the second organic polymer layer may include a polymer-based material. The polymer-based material may include any one material of polymethyl methacrylate (PMMA) and polystyrene (PS). The first separation layer may have a thickness ranging from 30 nm to 50 nm, and the first organic polymer layer may have a thickness that is greater than a thickness of the first dielectric layer. The second separation layer may have a thickness ranging from 30 nm to 50 nm, and the second organic polymer layer may have a thickness that is greater than a thickness of the second dielectric layer. Each of the first organic polymer layer and the second organic polymer layer may have a thickness ranging from 20 nm to 30 nm. A gate voltage applied to the gate electrode may have a first voltage range, a second voltage range, and a third voltage range as the gate voltage increases in a negative direction according to the operation of the first channel layer or the second channel layer. A channel may be formed in the second channel layer in the first voltage range, the channel of the second channel layer may be maintained in the third voltage range, and a channel may be formed in the first channel layer. A channel may be formed in the second channel layer in the first voltage range, and a current flowing in the second channel layer may be saturated in the second voltage range. A threshold voltage for forming a channel in the first voltage range and a threshold voltage for forming a channel in the third voltage range may have different values. In other example embodiments, a method of manufacturing a multi-level device includes forming a gate electrode on a substrate, forming a first separation layer including an organic insulating layer on the substrate and the gate electrode, forming a first channel layer on the first separation layer, forming a second separation layer including an organic insulating layer on the first channel layer, forming a second channel layer on the second separation layer, and forming a source electrode a