US-12622141-B2 - Display device

US12622141B2US 12622141 B2US12622141 B2US 12622141B2US-12622141-B2

Abstract

A display device includes a pixel circuit disposed on a substrate, and a display element on the pixel circuit. The pixel circuit includes a first thin-film transistor comprising a first semiconductor layer and a first gate electrode insulated from the first semiconductor layer, a second thin-film transistor comprising a second semiconductor layer and a second gate electrode insulated from the second semiconductor layer, the second semiconductor layer being connected to the first semiconductor layer and the first gate electrode, a first shielding layer overlapping the second semiconductor layer, and a second shielding layer overlapping the second semiconductor layer and stacked on the first shielding layer.

Inventors

Nayun Kwak
Chulkyu Kang
Daesuk Kim
Ilgoo Youn
DONGSUN LEE
Soyoung LEE
Jieun Lee
JunYoung Jo
Minhee Choi

Assignees

SAMSUNG DISPLAY CO., LTD.

Dates

Publication Date: 20260505
Application Date: 20250106
Priority Date: 20191204

Claims (20)

1 . An electronic device comprising: a display panel; and a window on the display panel, wherein the display panel comprises: a first transistor including a first semiconductor layer, a first gate electrode and a second gate electrode; a first shielding layer overlapping a portion of the first semiconductor layer, in a plan view; a capacitor including a first capacitor electrode and a second capacitor electrode on the first capacitor electrode; and a connection electrode connected to the first capacitor electrode and the first semiconductor layer, wherein the first semiconductor layer comprises a source area, a drain area, a first channel area, a second channel area and a middle area, the middle area is between the first channel area and the second channel area, wherein the first gate electrode overlaps the first channel area and the second gate electrode overlaps the second channel area in the plan view, wherein the first shielding layer overlaps the middle area of the first semiconductor layer, and wherein the connection electrode is connected to one of the source area and the drain area of the first semiconductor layer.
2 . The electronic device of claim 1 , wherein the first gate electrode and the second gate electrode are in a same layer.
3 . The electronic device of claim 1 , wherein the connection electrode is connected to the first capacitor electrode through an opening defined in the second capacitor electrode.
4 . The electronic device of claim 1 , further comprising: a driving transistor, wherein a part of the first capacitor electrode is a gate electrode of the driving transistor.
5 . The electronic device of claim 4 , wherein a semiconductor layer of the driving transistor is connected to the other one of the source area and the drain area of the first semiconductor layer.
6 . The electronic device of claim 4 , further comprising: a second transistor including a second semiconductor layer, a first gate electrode and a second gate electrode, wherein the second semiconductor layer comprises a source area, a drain area, a first channel area, a second channel area, and a middle area, wherein the middle area is between the first channel area and the second channel area, wherein the first gate electrode of the second transistor overlaps the first channel area of the second semiconductor layer and the second gate electrode of the second transistor overlaps the second channel area of the second semiconductor layer in a plan view, and wherein the connection electrode is connected to one of the source area and the drain area of the second semiconductor layer.
7 . The electronic device of claim 6 , further comprising: a first voltage line connected to the other one of the source area and the drain area of the second semiconductor layer.
8 . The electronic device of claim 1 , wherein the first shielding layer and the second capacitor electrode are on a same layer.
9 . The electronic device of claim 1 , further comprising: a second voltage line connected to the first shielding layer.
10 . The electronic device of claim 9 , further comprising: a second shielding layer overlapping the first shielding layer.
11 . The electronic device of claim 10 , wherein the second shielding layer is connected to the first shielding layer.
12 . The electronic device of claim 10 , wherein a part of the second voltage line is the second shielding layer.
13 . The electronic device of claim 10 , wherein the connection electrode and the second shielding layer are on a same layer.
14 . The electronic device of claim 1 , further comprising: a voltage line connected to the second capacitor electrode.
15 . The electronic device of claim 14 , wherein a voltage applied to the first shielding layer and a voltage applied to the voltage line are the same.
16 . The electronic device of claim 1 , wherein the first semiconductor layer of the first transistor comprises polysilicon.
17 . The electronic device of claim 1 , wherein the first shielding layer receives a constant voltage.
18 . The electronic device of claim 1 , further comprising: a scan line providing a scan signal to the first gate electrode and the second gate electrode of the first transistor, wherein the scan line crosses the connection electrode.
19 . The electronic device of claim 18 , wherein the scan line is in a space between the first shielding layer and the second capacitor electrode in the plan view.
20 . The electronic device of claim 1 , wherein the electronic device is one of a smartphone, a mobile phone, a smart watch, a navigation device, a game console, a television (TV), a head unit for a vehicle, a notebook computer, a laptop computer, a tablet computer, a personal media player (PMP), and a personal digital assistant (PDA).

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is a continuation of U.S. application Ser. No. 18/592,891 filed on Mar. 1, 2024, which is a continuation of U.S. application Ser. No. 18/161,434 filed on Jan. 30, 2023, issued as U.S. Pat. No. 11,950,460 issued on Apr. 2, 2024, which is a continuation of U.S. application Ser. No. 17/085,288 filed on Oct. 30, 2020, issued as U.S. Pat. No. 11,569,327 issued on Jan. 31, 2023, which claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2019-0160007, filed on Dec. 4, 2019, in the Korean Intellectual Property Office, the disclosure of each of which is herein incorporated by reference in its entirety. BACKGROUND 1. Field The present invention relates to a display device, and more particularly, to a display device including a thin-film transistor with a shielding layer. 2. Description of Related Art In general, display devices include a display element and a driving circuit for controlling electrical signals to be applied to the display element. The driving circuit includes a thin-film transistor (TFT), a storage capacitor, and a plurality of signal lines. To precisely control whether the display element emits light and a degree of emission of the display element, the number of TFTs to be electrically connected to one display element has increased. Thus, research into a way to solve the problem relating to high integration and power consumption of the display devices is briskly under way. SUMMARY One or more embodiments include a display device having enhanced display quality. However, this objective is just an example, and the scope of the present disclosure is not limited thereby. Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments of the disclosure. According to an exemplary embodiment of the present invention, a display device includes a pixel circuit disposed on a substrate, and a display element on the pixel circuit. The pixel circuit includes a first thin-film transistor comprising a first semiconductor layer and a first gate electrode insulated from the first semiconductor layer, a second thin-film transistor comprising a second semiconductor layer and a second gate electrode insulated from the second semiconductor layer, a first end of the second semiconductor layer being connected to a first end of the first semiconductor layer and a second end of the second semiconductor layer being connected to the first gate electrode, a first shielding layer overlapping the second semiconductor layer, and a second shielding layer overlapping the second semiconductor layer and stacked on the first shielding layer. The second gate electrode includes a first sub gate electrode and a second sub gate electrode. The second semiconductor layer including a first channel area and a second channel area. The second gate electrode includes a first sub gate electrode overlapping the first channel area and a second sub gate electrode overlapping the second channel area. The second shielding layer overlaps a part between the first channel area and the second channel area. The first sub gate electrode and the second sub gate electrode are located on the same layer. The first shielding layer and the second shielding layer comprise the same material. The first shielding layer and the second shielding layer comprise different materials from each other. The pixel circuit further includes a capacitor including an upper electrode and a part of the first gate electrode as a lower electrode, and a power supply voltage line connected to the upper electrode. The upper electrode overlaps the part of the first gate electrode. The first shielding layer, the second shielding layer and the upper electrode comprise the same material. The second shielding layer is a part of the power supply voltage line. The first shielding layer is connected to the power supply voltage line. The first shielding layer and the upper electrode comprise the same material. The second shielding layer and the power supply voltage line comprise the same material. The pixel circuit further includes a capacitor including an upper electrode and a part of the first gate electrode as a lower electrode, a power supply voltage line connected to the upper electrode, and a third shielding layer stacked on the second shielding layer. The second shielding layer is interposed between the first shielding layer and the third shielding layer. The upper electrode and the first shielding layer are located on the same layer. The upper electrode overlaps the part of the first gate electrode. The power supply voltage line and the second shielding layer are located on the same layer. The third shielding layer overlaps the second semiconductor layer. The display device further includes a data line connected to the pixel circuit. The data line and the third shielding layer are located o