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US-12622178-B2 - Semiconductor device and method for fabricating the same

US12622178B2US 12622178 B2US12622178 B2US 12622178B2US-12622178-B2

Abstract

A method for fabricating a semiconductor device includes the steps of first forming a spin orbit torque (SOT) layer on a substrate, forming a magnetic tunneling junction (MTJ) on the SOT layer, forming a first cap layer on the MTJ, forming a first inter-metal dielectric (IMD) layer on the first cap layer, forming a second cap layer on the first cap layer and the first IMD layer, forming a second IMD layer on the first cap layer, the first IMD layer, and the second cap layer, and then planarizing the first cap layer, the first IMD layer, the second cap layer, and the second IMD layer.

Inventors

  • Hui-Lin WANG

Assignees

  • UNITED MICROELECTRONICS CORP.

Dates

Publication Date
20260505
Application Date
20230417
Priority Date
20230313

Claims (17)

  1. 1 . A method for fabricating a semiconductor device, comprising: forming a spin orbit torque (SOT) layer on a substrate; forming a magnetic tunneling junction (MTJ) on the SOT layer; forming a first cap layer on the MTJ; forming a first inter-metal dielectric (IMD) layer on the first cap layer; and forming a second cap layer on the first cap layer and the first IMD layer and directly contacting a top surface and sidewalls of the first IMD layer after forming the first IMD layer.
  2. 2 . The method of claim 1 , further comprising: forming a second IMD layer on the first cap layer, the first IMD layer, and the second cap layer; and planarizing the first cap layer, the first IMD layer, the second cap layer, and the second IMD layer.
  3. 3 . The method of claim 1 , further comprising: performing a first etching process to pattern the first IMD layer; and performing a second etching process to pattern the first cap layer and the first IMD layer.
  4. 4 . The method of claim 3 , further comprising patterning the first IMD layer to expose a top surface of the first cap layer.
  5. 5 . The method of claim 3 , further comprising performing the second etching process so that top surfaces of the first cap layer and the first IMD layer are coplanar.
  6. 6 . The method of claim 1 , further comprising forming the second cap layer on a sidewall of the SOT layer.
  7. 7 . The method of claim 1 , further comprising forming the second cap layer on a sidewall of the first cap layer.
  8. 8 . The method of claim 1 , further comprising forming the second cap layer on a sidewall of the first IMD layer.
  9. 9 . The method of claim 1 , wherein the first cap layer and the second cap layer comprise same material.
  10. 10 . A semiconductor device, comprising: a spin orbit torque (SOT) layer on a substrate; a magnetic tunneling junction (MTJ) on the SOT layer; a first cap layer adjacent to the MTJ; a first inter-metal dielectric (IMD) layer adjacent to the first cap layer; and a second cap layer adjacent to the first cap layer and the first IMD layer, wherein, top surfaces of the first cap layer, the first IMD layer, and the second cap layer are coplanar.
  11. 11 . The semiconductor device of claim 10 , further comprising a second IMD layer adjacent to the second cap layer.
  12. 12 . The semiconductor device of claim 10 , wherein the second cap layer is on a sidewall of the first cap layer.
  13. 13 . The semiconductor device of claim 10 , wherein the first cap layer and the second cap layer comprise same material.
  14. 14 . A semiconductor device, comprising: a spin orbit torque (SOT) layer on a substrate; a magnetic tunneling junction (MTJ) on the SOT layer, wherein the MTJ comprises a circular shape in a top view; a first cap layer around the MTJ, wherein the first cap layer comprises a first ring in a top view and the first ring comprises a first circular ring; and a first inter-metal dielectric (IMD) layer around the first cap layer, wherein the first IMD layer comprises a second ring in a top view and the second ring comprises a second circular ring.
  15. 15 . The semiconductor device of claim 14 , further comprising a second cap layer around the first IMD layer, wherein the second cap layer comprises a third ring in a top view.
  16. 16 . The semiconductor device of claim 15 , further comprising a second IMD layer around the second cap layer.
  17. 17 . The semiconductor device of claim 14 , wherein the MTJ comprises an ellipse in a top view.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The invention relates to a semiconductor device and method for fabricating the same, and more particularly to a magnetoresistive random access memory (MRAM) and method for fabricating the same. 2. Description of the Prior Art Magnetoresistance (MR) effect has been known as a kind of effect caused by altering the resistance of a material through variation of outside magnetic field. The physical definition of such effect is defined as a variation in resistance obtained by dividing a difference in resistance under no magnetic interference by the original resistance. Currently, MR effect has been successfully utilized in production of hard disks thereby having important commercial values. Moreover, the characterization of utilizing GMR materials to generate different resistance under different magnetized states could also be used to fabricate MRAM devices, which typically has the advantage of keeping stored data even when the device is not connected to an electrical source. The aforementioned MR effect has also been used in magnetic field sensor areas including but not limited to for example electronic compass components used in global positioning system (GPS) of cellular phones for providing information regarding moving location to users. Currently, various magnetic field sensor technologies such as anisotropic magnetoresistance (AMR) sensors, GMR sensors, magnetic tunneling junction (MTJ) sensors have been widely developed in the market. Nevertheless, most of these products still pose numerous shortcomings such as high chip area, high cost, high power consumption, limited sensibility, and easily affected by temperature variation and how to come up with an improved device to resolve these issues has become an important task in this field. SUMMARY OF THE INVENTION According to an embodiment of the present invention, a method for fabricating a semiconductor device includes the steps of first forming a spin orbit torque (SOT) layer on a substrate, forming a magnetic tunneling junction (MTJ) on the SOT layer, forming a first cap layer on the MTJ, forming a first inter-metal dielectric (IMD) layer on the first cap layer, forming a second cap layer on the first cap layer and the first IMD layer, forming a second IMD layer on the first cap layer, the first IMD layer, and the second cap layer, and then planarizing the first cap layer, the first IMD layer, the second cap layer, and the second IMD layer. According to another aspect of the present invention, a semiconductor device includes a spin orbit torque (SOT) layer on a substrate, a magnetic tunneling junction (MTJ) on the SOT layer, a first cap layer adjacent to the MTJ, a first inter-metal dielectric (IMD) layer adjacent to the first cap layer, and a second cap layer adjacent to the first cap layer and the first IMD layer. According to yet another aspect of the present invention, a semiconductor device includes a spin orbit torque (SOT) layer on a substrate, a magnetic tunneling junction (MTJ) on the SOT layer, and a first cap layer around the MTJ. Preferably, the MTJ includes a circular shape in a top view and the first cap layer includes a first ring in a top view. These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1-8 illustrate a method for fabricating a MRAM device according to an embodiment of the present invention. FIG. 9 illustrates a structural view of a MRAM device according to an embodiment of the present invention. FIG. 10 illustrates a top view of the MRAM device and surrounding elements of FIG. 8. FIG. 11 illustrates a top view of the MRAM device and surrounding elements of FIG. 9. DETAILED DESCRIPTION Referring to FIGS. 1-8, FIGS. 1-8 illustrate a method for fabricating a semiconductor device, or more specifically a MRAM device according to an embodiment of the present invention. As shown in FIG. 1, a substrate 12 made of semiconductor material is first provided, in which the semiconductor material could be selected from the group consisting of silicon (Si), germanium (Ge), Si—Ge compounds, silicon carbide (SiC), and gallium arsenide (GaAs), and a MRAM region 14 and a logic region 40 are defined on the substrate 12. Active devices such as metal-oxide semiconductor (MOS) transistors, passive devices, conductive layers, and interlayer dielectric (ILD) layer 16 could also be formed on top of the substrate 12. More specifically, planar MOS transistors or non-planar (such as FinFETs) MOS transistors could be formed on the substrate 12, in which the MOS transistors could include transistor elements such as gate structures (for example metal gates) and source/drain region, spacer, epitaxial layer, and contact etch stop layer (CESL). The ILD layer 16 could be formed