US-12622182-B2 - Semiconductor device and method for forming the same

US12622182B2US 12622182 B2US12622182 B2US 12622182B2US-12622182-B2

Abstract

A semiconductor device and a method for forming the same are provided. The semiconductor device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first electrode, a second electrode on one side of the first electrode, and a resistive switching film between the first electrode and the second electrode. The first electrode, the resistive switching film and the second electrode are arranged along the first direction. The second semiconductor structure includes a first via and a first metal layer on the first via along a second direction and electrically connected to the first via. The first direction is perpendicular to the second direction. An upper surface of the first electrode, an upper surface of the second electrode, an upper surface of the resistive switching film and an upper surface of the first metal layer are coplanar.

Inventors

Yen-Min TING
Chuan-Fu Wang
Yu-Huan Yeh

Assignees

UNITED MICROELECTRONICS CORP.

Dates

Publication Date: 20260505
Application Date: 20221205
Priority Date: 20221018

Claims (15)

1 . A semiconductor device, comprising: a first semiconductor structure and a second semiconductor structure disposed on one side of the first semiconductor structure along a first direction, wherein the first semiconductor structure comprises: a first electrode, a second electrode on one side of the first electrode, and a resistive switching film between the first electrode and the second electrode, wherein the first electrode, the resistive switching film and the second electrode are arranged along the first direction, wherein the second semiconductor structure comprises: a first via; a first metal layer on the first via along a second direction and electrically connected to the first via, wherein the first direction is perpendicular to the second direction; and a second metal layer below the first via and electrically connected to the first via, wherein an upper surface of the first electrode, an upper surface of the resistive switching film, an upper surface of the second electrode, and an upper surface of the first metal layer are coplanar.
2 . The semiconductor device according to claim 1 , wherein the first semiconductor structure comprises a second via and a third via, the second via is on the upper surface of the first electrode, the third via is on the upper surface of the second electrode, and wherein the second via, the second semiconductor structure and the third via are electrically connected to each other.
3 . The semiconductor device according to claim 1 , wherein the first semiconductor structure is in a memory region and the second semiconductor structure is in a logic region.
4 . The semiconductor device according to claim 1 , wherein the resistive switching film directly contacts the first electrode and the second electrode.
5 . The semiconductor device according to claim 1 , wherein the first semiconductor structure comprises a first barrier film between the first electrode and the resistive switching film and a second barrier film between the second electrode and the resistive switching film.
6 . The semiconductor device according to claim 1 , wherein a lower surface of the first electrode and a lower surface of the resistive switching film are coplanar.
7 . The semiconductor device according to claim 1 , wherein a height of the first electrode is greater than a height of the resistive switching film.
8 . The semiconductor device according to claim 1 , further comprising: a first dielectric layer; a second dielectric layer; and a third dielectric layer, wherein the first dielectric layer, the second dielectric layer and the third dielectric layer are stacked along the second direction, wherein the first electrode, the resistive switching film and the second electrode are in the third dielectric layer and above the second dielectric layer.
9 . The semiconductor device according to claim 8 , wherein the first via is in the second dielectric layer and the third dielectric layer, and the first metal layer is in the third dielectric layer and above the second dielectric layer.
10 . The semiconductor device according to claim 9 , wherein the second metal layer is in the first dielectric layer.
11 . The semiconductor device according to claim 10 , wherein the first semiconductor structure comprises a third metal layer and a fourth metal layer in the first dielectric layer, wherein the third metal layer at least partially overlaps the first electrode in the second direction, and the fourth metal layer at least partially overlaps the second electrode in the second direction.
12 . The semiconductor device according to claim 11 , wherein the first semiconductor structure is in a memory region and the second semiconductor structure is in a logic region.
13 . The semiconductor device according to claim 1 , wherein the second semiconductor structure comprises a barrier film on an outer surface of the first metal layer.
14 . The semiconductor device according to claim 13 , wherein the second semiconductor structure comprises another barrier film on an outer surface of the second metal layer.
15 . The semiconductor device according to claim 14 , wherein the second semiconductor structure comprises a barrier film on an outer surface of the first metal layer.

Description

This application claims the benefit of Taiwan application Serial No. 111139464, filed Oct. 18, 2022, the subject matter of which is incorporated herein by reference. BACKGROUND Technical Field The present disclosure relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device including a resistive switching film and a method for manufacturing the same. Description of the Related Art Resistance random access memory (RRAM) is the promising candidate for the next generation of non-volatile memory. A resistance random access memory stores data within a resistive switching film. With applying appropriate voltage, the resistive switching film can be switched from a high resistance state to a low resistance state repeatedly to store the digital information. However, there are still several important issues unaddressed in the development of resistance random access memory, among which, how to reduce the critical dimension of resistance random access memory is a big concern. It is important to provide technology for semiconductor devices including resistive memory devices with reduced critical dimensions. SUMMARY The present disclosure relates to a semiconductor device and a method for manufacturing the same. According to an embodiment of the present disclosure, a semiconductor device is provided. The semiconductor device includes a first semiconductor structure and a second semiconductor structure disposed on one side of the first semiconductor structure along a first direction. The first semiconductor structure includes a first electrode, a second electrode on one side of the first electrode and a resistive switching film between the first electrode and the second electrode. The first electrode, the resistive switching film and the second electrode are arranged along the first direction. The second semiconductor structure includes a first via and a first metal layer. The first metal layer is on the first via along a second direction and electrically connected to the first via. The first direction is perpendicular to the second direction. An upper surface of the first electrode, an upper surface of the resistive switching film, an upper surface of the second electrode, and an upper surface of the first metal layer are coplanar. According to another embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided. The method includes the steps of providing a substrate, forming a resistive switching film in the substrate, and forming a first electrode and a second electrode on opposite sides of the resistive switching film. The above and other embodiments of the disclosure will become better understood with regard to the following detailed description of the non-limiting embodiment(s). The following description is made with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates a schematic sectional view of a semiconductor device according to an embodiment of the present disclosure. FIG. 2 illustrates a schematic sectional view of a semiconductor device according to another embodiment of the present disclosure. FIGS. 3-9 illustrate a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. FIGS. 10-17 illustrate a method for manufacturing a semiconductor device according to another embodiment of the present disclosure. DETAILED DESCRIPTION Various embodiments will be described more fully hereinafter with reference to accompanying drawings, which are provided for illustrative and explaining purposes rather than a limiting purpose. For clarity, the components may not be drawn to scale. In addition, some components and/or reference numerals may be omitted from some drawings. It is contemplated that the elements and features of one embodiment can be beneficially incorporated in another embodiment without further recitation. Referring to FIG. 1, FIG. 1 illustrates a schematic sectional view of a semiconductor device 10 according to an embodiment of the present disclosure. The semiconductor device 10 includes a substrate 100. The substrate 100 includes a first dielectric layer 101, a second dielectric layer 102 and a third dielectric layer 103 stacked along a second direction D2. A portion of the substrate 100 can be defined as a memory region 11, and another portion of the substrate 100 can be defined as a logic region 12. The memory region 11 and the logic region 12 may be disposed adjacent to each other. The logic region 12 may be disposed around the memory region 11. The semiconductor device 10 includes a first semiconductor structure 110 and a second semiconductor structure 120 in the substrate 100. The first semiconductor structure 110 is located in the memory region 11. The second semiconductor structure 120 is located in the logic region 12. The second semiconductor structure 120 is disposed on one side of the first semiconductor structur