US-12622183-B2 - Phase change memory (PCM) cell structure having heating layer and formation method therefor

US12622183B2US 12622183 B2US12622183 B2US 12622183B2US-12622183-B2

Abstract

A semiconductor structure includes a substrate and a phase-change memory cell located on the substrate. The phase-change memory cell includes a phase-change material layer and a heating layer. The heating layer is located between the phase-change material layer and the substrate, and includes a first portion composed of a first conductive material and a second portion composed of a second conductive material. The first portion surrounds at least a sidewall of the second portion.

Inventors

Yu-Cheng Liao

Assignees

CHANGXIN MEMORY TECHNOLOGIES, INC.

Dates

Publication Date: 20260505
Application Date: 20230117
Priority Date: 20220704

Claims (6)

1 . A method for forming a semiconductor structure, comprising: providing a substrate; forming a phase-change memory cell on the substrate, wherein the phase-change memory cell comprises a phase-change material layer, a heating layer and a diode, the heating layer being located between the phase-change material layer and the substrate, and the heating layer comprises a first portion composed of a first conductive material and a second portion composed of a second conductive material, and the first portion surrounds at least a sidewall of the second portion; wherein the forming a phase-change memory cell on the substrate comprises: forming, on the substrate, the diode perpendicular to the substrate, including: forming a first ion implantation layer on the substrate; forming a second ion implantation layer on the first ion implantation layer, including: forming a lower-layer second ion implantation layer; and forming an upper-layer second ion implantation layer on the lower-layer second ion implantation layer, wherein an ion concentration of the upper-layer second ion implantation layer is different from an ion concentration of the lower-layer second ion implantation layer, an ion type of the first ion implantation layer is opposite to an ion type of the second ion implantation layer; and etching the first ion implantation layer and the second ion implantation layer to form a first ion implantation structure and a second ion implantation structure, to form the diode; forming the heating layer on the diode; and forming the phase-change material layer on the heating layer.
2 . The method of claim 1 , further comprising: forming a thermal insulation layer to cover a sidewall and at least partial upper surface of the phase-change memory cell.
3 . The method of claim 1 , wherein forming the heating layer on the diode comprises: forming a first conductive layer on the second ion implantation layer; etching the first conductive layer to form a plurality of groove structures; filling the second conductive material in the groove structures to form the second portion; and etching partial first conductive layer other than the second portion, to form the first portion.
4 . The method of claim 1 , wherein the substrate comprises a backing substrate, a buried oxide layer located on the backing substrate, and a top-layer silicon located on the buried oxide layer; and wherein the method further comprises: before forming the phase-change memory cell on the substrate, doping the top-layer silicon to form a doped layer, wherein the doped layer comprises an N well layer, a P well layer and a third ion implantation layer; etching the doped layer to form a plurality of doped structures, wherein the doped structure comprises N well, a P well and a third ion implantation structure, and the third ion implantation structure is connected to the first ion implantation structure; and forming a shallow trench isolation structure, to fill a groove between adjacent doped structures.
5 . The method of claim 4 , further comprising: forming an interlayer dielectric layer, and filling the interlayer dielectric layer among a plurality of phase-change memory cells; and forming a first conductive structure, to penetrate the interlayer dielectric layer and connect the third ion implantation structure.
6 . The method of claim 5 , further comprising: forming a second conductive structure to connect to the phase-change memory cell, wherein the first conductive structure is connected to a first conductive wire that extends in a first direction parallel to the substrate, the second conductive structure is connected to a second conductive wire that extends in a second direction parallel to the substrate, and the second direction intersects with the first direction.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This is a continuation of International Patent Application No. PCT/CN2022/108178 filed on Jul. 27, 2022, which claims priority to Chinese Patent Application No. 202210786445.1 filed on Jul. 4, 2022. The disclosures of the above-referenced applications are hereby incorporated by reference in their entirety. BACKGROUND A Phase Change Memory (PCM) is a novel memory that uses a huge resistance difference between a crystalline phase-change material and an amorphous phase-change material to achieve information storage. The amorphous phase-change material has high resistance, of which molecular structure is in a disordered state. The crystalline phase-change material has low resistance, of which molecular structure is in an ordered state. A resistance difference between the phase-change materials in two states generally reaches 2 orders of magnitude. By means of joule heat induced by current, the phase-change material can be rapidly transformed between two resistance states (i.e., a high resistance state and a low resistance state). Since the PCM has the advantages of being strong in stability, low in power consumption, high in storage density, and compatible with a conventional CMOS process, more and more researchers and enterprises pay more attention to the PCM. The PCM is considered to be one of the most potential next-generation non-volatile memories with its huge advantages. How to improve the storage density and storage speed of the PCM has become an urgent problem to be resolved. SUMMARY The disclosure relates to the technical field of semiconductors, and specifically, to a semiconductor structure and a formation method therefor, and a memory. According to a first aspect, an embodiment of the disclosure provides a semiconductor structure. The semiconductor structure includes a substrate and a phase-change memory cell. The phase-change memory cell is located on the substrate. The phase-change memory cell includes a phase-change material layer and a heating layer. The heating layer is located between the phase-change material layer and the substrate. The heating layer includes a first portion composed of a first conductive material and a second portion composed of a second conductive material. The first portion surrounds at least a sidewall of the second portion. According to a second aspect, an embodiment of the disclosure provides a method for forming a semiconductor structure. The method includes the following operations. A substrate is provided. A phase-change memory cell is formed on the substrate. The phase-change memory cell includes a phase-change material layer and a heating layer. The heating layer is located between the phase-change material layer and the substrate. The heating layer includes a first portion composed of a first conductive material and a second portion composed of a second conductive material. The first portion surrounds at least a sidewall of the second portion. According to a third aspect, an embodiment of the disclosure further provides a memory. The memory includes a memory cell array and a peripheral circuit structure located above or outside the memory cell array, where the memory cell includes the semiconductor structure described in any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of a phase-change memory according to some embodiments. FIG. 2 is a first schematic cross-sectional view of a semiconductor structure according to an embodiment of the disclosure. FIG. 3 is a second schematic cross-sectional view of a semiconductor structure according to an embodiment of the disclosure. FIG. 4 is a third schematic cross-sectional view of a semiconductor structure according to an embodiment of the disclosure. FIG. 5 is a first schematic top cross-sectional view of a heating layer according to an embodiment of the disclosure. FIG. 6 is a second schematic top cross-sectional view of a heating layer according to an embodiment of the disclosure. FIG. 7 is a third schematic top cross-sectional view of a heating layer according to an embodiment of the disclosure. FIG. 8 is a fourth schematic top cross-sectional view of a heating layer according to an embodiment of the disclosure. FIG. 9 is a first schematic cross-sectional view of a semiconductor structure according to an embodiment of the disclosure. FIG. 10 is a second schematic cross-sectional view of a semiconductor structure according to an embodiment of the disclosure. FIG. 11 is a third schematic cross-sectional view of a semiconductor structure according to an embodiment of the disclosure. FIG. 12 is a fourth schematic cross-sectional view of a semiconductor structure according to an embodiment of the disclosure. FIG. 13 is a fifth schematic cross-sectional view of a semiconductor structure according to an embodiment of the disclosure. FIG. 14 is a flowchart of a method for forming a semiconductor structure according to an embodiment of the di