US-12622185-B2 - Method for manufacturing semiconductor silicon wafer composed of silicon wafer substrate and silicon monocrystalline epitaxial layer

Abstract

Provided is a method for manufacturing a semiconductor silicon wafer capable of inhibiting P-aggregation defects (Si—P defects) and SF in an epitaxial layer. The method includes a step of forming a silicon oxide film with a thickness of at least 300 nm or thicker only on the backside of the silicon wafer substrate by the CVD method at a temperature of 500° C. or lower after the step of forming the silicon oxide film, a step of heat treatment where the substrate is kept in an oxidizing atmosphere at a constant temperature of 1100° C. or higher and 1250° C. or lower for 30 minutes or longer and 120 minutes or shorter after the heat treatment, a step of removing surface oxide film formed on the front surface of the substrate, and a step of depositing a silicon monocrystalline epitaxial layer on the substrate after the step of removing the surface oxide film.

Inventors

• Takeshi Senda
• Haruo Sudo

Assignees

• GLOBALWAFERS JAPAN CO., LTD.

Dates

Publication Date

20260505

Application Date

20210216

Priority Date

20200219

Claims (2)

1. 1 . A method for manufacturing a semiconductor silicon wafer with a silicon monocrystalline epitaxial layer, wherein a silicon monocrystalline epitaxial film with reduced SF is formed on the front surface side of a substrate sliced from a silicon single crystal ingot that is grown using the Czochralski method, the method comprising: a step of manufacturing substrates, being doped with phosphorus, having resistivity being adjusted to be 1.05 mΩ·cm or less, a concentration of solid-solution oxygen of 0.9×10 18 atoms/cm 3 or less, and sliced such that the slicing angle against the primary plane orientation falls in a range of 0.1 degrees to 0.4 degree; a step of forming a silicon oxide film with a thickness of at least 300 nm or thicker only on a backside of the silicon wafer substrate containing Si—P (silicon phosphorus) defects by the CVD method at a temperature of 500° C. or lower; a step of heat treatment, after the step of forming a silicon oxide film, in which the substrate, only on the backside of which a silicon oxide film is formed, is kept in an oxidizing atmosphere at a constant temperature of more than 1100° C. or higher and 1250° C. or lower for 30 minutes or longer and 120 minutes or shorter such that for the substrate after the heat treatment in the oxidizing atmosphere, a thickness of a surface thermal oxide film formed on the surface of the substrate is 20 nm or more to 150 nm or less, and a concentration of phosphorus (P) to a depth of 300 nm from the substrate surface is 7×10 19 atoms/cm 3 or less; a step of removal of a front surface oxide film, after the step of heat treatment, in which a thermal oxide film formed on the front surface of the substrate is removed, wherein the thickness of the CVD oxide film on the backside of the substrate remains at 300 nm or more after the step of removal of the surface thermal oxide film; and a step of deposition of a silicon monocrystalline epitaxial layer on the front surface of the substrate from which the oxide film is removed, after the step of removing the surface oxide film.
2. 2 . The method for manufacturing a semiconductor silicon wafer in claim 1 , wherein the substrate manufactured from the silicon single crystal ingot contains Si—P defects that are formed by aggregation of phosphorus during the growth of the silicon single crystal ingot, a maximum side length of the Si—P defects is less than 100 nm, and a concentration of the Si—P defects is less than 1×10 12 /cm 3 .

Description

TECHNICAL FIELD The present invention relates to a method for manufacturing semiconductor silicon wafers, specifically relates to a method for manufacturing a semiconductor silicon wafer composed of a silicon wafer substrate and a silicon monocrystalline epitaxial layer formed thereon, where the silicon wafer substrate is doped with phosphorus P and has a concentration of solid-solution oxygen adjusted to be 0.9×1018 atoms/cm3 or less and a resistivity adjusted to be 1.05 mΩ·cm or less. BACKGROUND ART The substrate resistivity of the most advanced epitaxial wafer for power MOS devices is 1.00 mΩ·cm or less. To reduce the substrate resistivity further, an increase in dopant concentration is necessary. The n-type dopant species, therefore, are being transitioned from arsenic (As) or antimony (Sb) to phosphorus (P) having relatively low volatility, and its concentration is approximately 1×1020 atoms/cm3. As recited in patent literature PTL 1 to PTL 3, growing an epitaxial layer with the increased dopant concentration causes to generate stacking faults (hereinafter also referred to as SF) in an epitaxial layer. In particular, SF are apt to occur in the case of substrates having a resistivity of 1.1 mΩ·cm or less. It is reported in PTL 1 to PTL 3 that the reason is speculated that the crystal defects originating from the SF are defects due to clusters of phosphorus (P) and oxygen (O). Further, PTLs also report technologies for the inhibition of crystal defects in the processes of heat treatment and epitaxial growth. Specifically, clusters of phosphorus and oxygen (micro precipitates) are formed when the silicon wafer doped with phosphorus is heated. After that, by performing heat treatment in a hydrogen gas atmosphere (hereinafter referred to as hydrogen baking processing) aiming to remove the natural oxide film on the silicon wafer surface, clusters are selectively etched to become fine pits due to the difference in etching speed between the outermost surface layer of the silicon wafer and the clusters. The PTL 1 and 2 report that it is speculated that when an epitaxial layer is grown on a silicon wafer where the minute pits are formed, SF originating from the minute pits occurs in the epitaxial layer. Patent Literature PTL 1 discloses a method for manufacturing an epitaxial silicon wafer including: a step of forming an oxide film on the back surface of a silicon wafer cut out from a single crystal ingot manufactured by the CZ method, a step of removing the oxide film existing on the outer circumference of the silicon wafer, a step of argon annealing in which the silicon wafer is heat-treated at a temperature of 1200° C. or higher and 1220° C. or lower in an argon atmosphere, a step of hydrogen baking process in which the wafer after the argon annealing step is heat-treated for 30 seconds or more and 300 seconds or less at a temperature of 1050° C. or more and 1200° C. or less in a hydrogen atmosphere, and a step of growing an epitaxial layer on the surface of the silicon wafer after the hydrogen baking process. The document PTL 1 further recites that SF in the epitaxial layer can be inhibited by the above method. PTL 2 also recites, similar to PTL 1, a method for manufacturing an epitaxial silicon wafer that inhibits the occurrence of SF in the epitaxial layer. CITATION LIST Patent Literature PTL 1: Japanese Patent No. 5845143PTL 2: Japanese Patent No. 6477210 SUMMARY OF INVENTION Technical Problem It is clarified through the present inventors' experiments that the countermeasures described in PTL1 and 2 are not sufficient to reduce SF. In their experiments, monocrystalline silicon wafers with a diameter of 200 mm doped with phosphorus having a resistivity of 0.8 mΩ·cm and oxygen concentration of 0.8×1018/cm3 grown by the Chzochralski method are heat-treated in an argon atmosphere at 1200° C. for one hour. Successively, after hydrogen baking at 1180° C. for 60 seconds in a hydrogen atmosphere, an epitaxial layer was grown to a thickness of 3 μm on the wafer surface. Then the number of LPDs of 90 nm in size or larger is evaluated with SP-1 operated in DCN mode manufactured by KLA-Tencor Corporation, and the density of LPDs originating from SF is at least 10 or more/cm2 was observed; this means not less than 3,140 per wafer. As is shown above, it is difficult to inhibit the formation even though the concentration of the solid-solution oxygen in the surface layer is sufficiently reduced by the heat treatment under the argon gas atmosphere. To solve the above problem, the present inventors have intensively studied the inhibition of SF in an epitaxial laver. The present inventors found that when the oxygen concentration in the silicon crystal is 0.9×1013 atoms/cm3 or less, the type of defects including phosphorus is Si—P aggregation defects (Si—P defects) formed of phosphorus of an atomic % order and silicon. Further, it is found that P-aggregation defects (Si—P defects) have internal excess Si planes (SF) therein