US-12622188-B2 - Semiconductor structure and method

Abstract

This disclosure relates to a semiconductor structure ( 100 ), comprising a crystalline silicon substrate ( 110 ), having a surface ( 111 ), and a crystalline silicon oxide superstructure ( 120 ) on the surface ( 111 ) of the silicon substrate ( 110 ), the silicon oxide superstructure ( 120 ) having a thickness of at least two molecular layers and a (1×1) plane structure using Wood's notation.

Inventors

• Pekka Laukkanen
• Juha-Pekka LEHTIÖ
• Zahra JAHANSHAH RAD
• Mikhail KUZMIN
• Marko Punkkinen
• Antti LAHTI
• Kalevi KOKKO

Assignees

• TURUN YLIOPISTO

Dates

Publication Date

20260505

Application Date

20200423

Priority Date

20190426

Claims (15)

1. 1 . A semiconductor structure, comprising a crystalline silicon substrate, having a surface, and a superstructure on the surface of the silicon substrate, wherein the superstructure comprises silicon oxide that is crystalline, the superstructure having a thickness of at least two molecular layers and a (1×1) plane structure using Wood's notation, wherein the superstructure is formed on the surface as crystalline silicon oxide with no trace amounts of elements other than Si or O as impurities by: providing the silicon substrate, having a substantially clean deposition surface in a vacuum chamber; heating the silicon substrate to an oxidation temperature T O in a range from 100 to 530° C.; and while keeping the silicon substrate at the oxidation temperature, supplying molecular oxygen, O 2 , into the vacuum chamber with an oxidation pressure P O in a range from 1×10 −8 millibars, mbar, to 1×10 −4 mbar and an oxygen dose D O in a range from 0.1 to 10 000 Langmuir, L.
2. 2 . A semiconductor structure according to claim 1 , wherein the surface is a silicon {100}, a silicon {111}, or a silicon {110} surface.
3. 3 . A semiconductor structure according to claim 1 , wherein the superstructure has a thickness greater than or equal to 1 nanometers, nm, and/or less than or equal to 10 nm.
4. 4 . A semiconductor structure according to claim 1 , further comprising a dielectric capping layer on the superstructure.
5. 5 . A semiconductor structure according to claim 4 , wherein the capping layer comprises a dielectric material with a relative permittivity, κ, greater than or equal to 10.
6. 6 . A method for forming a semiconductor structure, comprising a crystalline silicon substrate and a crystalline silicon oxide superstructure on the silicon substrate, the method comprising: providing the silicon substrate, having a substantially clean deposition surface in a vacuum chamber; heating the silicon substrate to an oxidation temperature T O in a range from 100 to 530° C.; and while keeping the silicon substrate at the oxidation temperature, supplying molecular oxygen, O 2 , into the vacuum chamber with an oxidation pressure P O in a range from 1×10 −8 millibars, mbar, to 1×10 −4 mbar and an oxygen dose D O in a range from 0.1 to 10 000 Langmuir, L; whereby the crystalline silicon oxide superstructure, made of silicon oxide that is crystalized with no trace amounts of elements other than Si or O as impurities, is formed on the deposition surface, the superstructure having a thickness of at least two molecular layers and a (1×1) plane structure using Wood's notation.
7. 7 . A method according to claim 6 , wherein the deposition surface is a silicon {100}, a silicon {111}, or a silicon {110} surface.
8. 8 . A method according to claim 6 , wherein the oxidation temperature T O lies in a range from 150 to 520° C.
9. 9 . A method according to claim 6 , wherein the oxidation pressure P O lies in a range from 1×10 −8 mbar to 1×10 −5 mbar.
10. 10 . A method according to claim 6 , wherein the oxygen dose D O lies in a range from 1 to 1000 L.
11. 11 . A method according to claim 6 , wherein the molecular oxygen O 2 is supplied into the vacuum chamber for an oxidation period with an oxidation duration, t O , in a range from 0.5 seconds, s, to 30 minutes, min.
12. 12 . A method according to claim 6 , wherein the process of providing the silicon substrate comprises cleaning the deposition surface for removing possible native oxide and/or other impurities therefrom before the process of supplying molecular oxygen.
13. 13 . A method according to claim 12 , wherein the process of cleaning the deposition surface comprises an RCA cleaning step and, following the RCA cleaning step, a pre-annealing step at a pre-annealing temperature, T A , in a range from 200 to 300° C. and a pre-annealing pressure, P A , less than or equal to 1×10 −4 mbar for a pre-annealing period with a pre-annealing duration, t A , greater than or equal to 1 min.
14. 14 . A method according to claim 6 , further comprising depositing a dielectric capping layer on the silicon oxide superstructure.
15. 15 . A method according to claim 6 , having a maximum processing temperature T max less than or equal to 500° C.

Description

RELATED APPLICATIONS The present application is a U.S. National Stage application under 35 USC 371 of PCT Application Serial No. PCT/FI2020/050265, filed on 23 Apr. 2020; which claims priority to FI patent application No. 20195341, filed on 26 Apr. 2019, the entirety of each which are incorporated herein by reference. FIELD OF TECHNOLOGY This disclosure concerns semiconductor structures and methods for forming thereof. In particular, this disclosure concerns silicon oxide structures for surface passivation of silicon-based semiconductor devices. BACKGROUND Silicon is the most common substrate material in conventional semiconductor devices, such as transistors, capacitors, diodes, photodiodes, and other types of microelectronic and photonic components. In all such devices, interface quality of a substrate is of utmost importance. In conventional devices, surfaces of silicon substrates are typically passivated by growing a layer of thermal oxide onto said surfaces. However, known oxidation methods result in amorphous silicon oxide layers. The amorphousness of such oxide layers necessarily leads to existence of defect states at passivated silicon surfaces. This inevitably deteriorates performance of devices fabricated onto conventionally passivated substrates. Moreover, conventional oxidation procedures rely on relatively high processing temperatures, which may deteriorate properties of silicon substrates and/or structures fabricated onto such substrates. In light of such challenges, it may be desirable to develop new solutions related to passivation of silicon surfaces. In US 20060003500 A1, a method is disclosed where one atomic layer of oxygen is deposited self-limitedly on an existing silicon surface to form one molecular layer of crystalline silicon dioxide. SUMMARY This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. According to a first aspect, a semiconductor structure is provided. The semiconductor structure comprises a crystalline silicon substrate, having a surface, and a crystalline silicon oxide superstructure on the surface of the silicon substrate, the silicon oxide superstructure having a thickness of at least two molecular layers and a (1×1) plane structure using Wood's notation. According to a second aspect, a method for forming a semiconductor structure, comprising a crystalline silicon substrate and a crystalline silicon oxide superstructure on the silicon substrate, is provided. The method comprises providing the silicon substrate, having a substantially clean deposition surface in a vacuum chamber; heating the silicon substrate to an oxidation temperature TO in a range from 100 to 530° C.; and, while keeping the silicon substrate at the oxidation temperature, supplying molecular oxygen (O2) into the vacuum chamber with an oxidation pressure PO in a range from 1×10−8 millibars (mbar) to 1×10−4 mbar and an oxygen dose DO in a range from 0.1 to 10 000 Langmuir (L). Through this, the crystalline silicon oxide superstructure is formed on the deposition surface, the silicon oxide superstructure having a thickness of at least two molecular layers and a (1×1) plane structure using Wood's notation. According to a third aspect, the present disclosure relates to use of a crystalline silicon oxide superstructure, having a (1×1) plane structure using Wood's notation, in a semiconductor structure for passivation of a surface of a crystalline silicon substrate. In an embodiment of the third aspect, the semiconductor structure is a semiconductor structure in accordance with the first aspect or any embodiment of the first aspect. It is specifically to be understood that a crystalline silicon oxide superstructure may be used according to the third aspect for passivation of a surface of a crystalline silicon substrate in a semiconductor structure according to the first aspect or any embodiment of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS The present disclosure will be better understood from the following Detailed Description read in light of the accompanying drawings, wherein: FIG. 1 shows a cross-sectional view of a semiconductor structure, FIG. 2 illustrates a method for forming a semiconductor structure, and FIGS. 3a, 3b, and 3c depict scanning tunneling microscopy images of a silicon sample. FIGS. 4a and 4b show scanning tunneling microscopy images of another silicon sample. Unless specifically stated to the contrary, any drawing of the aforementioned drawings may be not drawn to scale such that any element in said drawing may be drawn with inaccurate proportions with respect to other elements in said drawing in order to emphasize certain structural aspects of the embodiment of said drawing. Moreover, corresponding elem