US-12622194-B2 - Semiconductor structure including devices with different channel lengths, and method for manufacturing the same

US12622194B2US 12622194 B2US12622194 B2US 12622194B2US-12622194-B2

Abstract

A method for manufacturing a semiconductor structure includes: forming an interconnect level structure having a first device region, a first side region aside the first device region, a second device region and a second side region aside the second device region; forming a dielectric layer over the interconnect structure, the dielectric layer including a first dielectric portion, a second dielectric portion, a first patterned portion and a second patterned portion that are respectively formed over the first device region, the second device region, the first side region, and the second side region, the first patterned portion and the second patterned portion being formed with different patterns; performing a planarization process on the dielectric layer; forming first recesses and second recesses respectively in the planarized first dielectric portion and the planarized second dielectric portion; and forming contact portion respectively in the first recesses and the second recesses.

Inventors

Tzu-Hsiang HSU
Sun-Yi Chang
Katherine H. Chiang

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date: 20260505
Application Date: 20230627

Claims (20)

1 . A method for manufacturing a semiconductor structure, comprising: forming an interconnect level structure having a first device portion including a first device region and a first side region aside the first device region, and a second device portion displaced apart from the first device portion, and including a second device region and a second side region aside the second device region; forming a dielectric layer over the interconnect structure, the dielectric layer including a first dielectric portion formed over the first device region, a second dielectric portion formed over the second device region, a first patterned portion formed over the first side region, and a second patterned portion formed over the second side region, the first patterned portion and the second patterned portion being formed with different patterns; performing a planarization process on the dielectric layer such that a top surface of the planarized first dielectric portion is at a level different from a level of a top surface of the planarized second dielectric portion; forming first recesses in the planarized first dielectric portion and second recesses in the planarized second dielectric portion, a distance between bottoms of two adjacent ones of the first recesses being different from a distance between bottoms of two adjacent ones of the second recesses; and forming contact portions respectively in the first recesses and the second recesses.
2 . The method according to claim 1 , wherein: the interconnect level structure further includes a logic area spaced apart from the first device region and the second device region; the dielectric layer is formed over the first device portion, the second device portion and the logic area; and the planarization process is performed over the first device portion, the second device portion and the logic area.
3 . The method according to claim 1 , wherein forming the dielectric layer includes: forming a dielectric material layer over the interconnect level structure; forming a shielding mask over the dielectric material layer, the shielding mask covering a first portion of the dielectric material layer and partially exposing a second portion of the dielectric material layer; and patterning the dielectric material layer through the shielding mask such that the first portion of the dielectric material layer covered by the shielding mask serves as the first dielectric portion, the second dielectric portion and the first patterned portion, and such that the second portion of the dielectric material layer is patterned to form the second patterned portion.
4 . The method according to claim 1 , wherein in forming the dielectric layer, each of the first dielectric portion and the second dielectric portion is formed to have a planar surface opposite to a corresponding one of the first device region and the second device region.
5 . The method according to claim 4 , wherein the planar surfaces of the first dielectric portion and the second dielectric portion are flush with each other.
6 . The method according to claim 1 , wherein in forming the dielectric layer, the first patterned portion has at least one dummy insertion, and the second patterned portion has at least one dummy insertion.
7 . The method according to claim 6 , wherein in forming the dielectric layer, a configuration of the at least one dummy insertion of the first patterned portion is different from a configuration of the at least one dummy insertion of the second patterned portion.
8 . The method according to claim 1 , wherein the first recesses and the second recesses are formed to have different profiles.
9 . A method for manufacturing a semiconductor structure, comprising: forming a base element; forming a dielectric layer over the base element, the dielectric layer having a first plain portion, a first patterned portion aside the first plain portion, a second plain portion spaced apart from the first plain portion, and a second patterned portion aside the second plain portion, the second patterned portion having a pattern different from a pattern of the first patterned portion; performing a planarization process on the dielectric layer such that a top surface of the planarized first plain portion is at a level different from a level of a top surface of the planarized second plain portion; forming first recesses in the planarized first plain portion and forming second recesses in the planarized second plain portion, the first recesses having a profile different from a profile of the second recesses; and filling the first recesses and the second recesses with filling elements.
10 . The method according to claim 9 , wherein in the planarization process, a height of the planarized first plain portion is different from a height of the planarized second plain portion.
11 . The method according to claim 9 , wherein in forming the dielectric layer, top surfaces of the first plain portion and the second plain portion are flush with each other.
12 . The method according to claim 9 , wherein forming the first recesses and the second recesses includes: forming a patterned protection layer over the planarized dielectric layer such that the planarized first patterned portion and the planarized second patterned portion are covered by the patterned protection layer, and the planarized first plain portion and the planarized second plain portion are exposed from the patterned protection layer; forming a patterned mask layer over the patterned protection layer and the planarized dielectric layer, the patterned mask layer having openings each having the same width; and patterning the planarized first plain portion and the planarized second plain portion through the patterned mask layer such that portions of the planarized first plain portion and the planarized second plain portion which are exposed from the openings are removed to form the first recesses and the second recesses.
13 . The method according to claim 12 , wherein top widths of the first recesses and the second recesses are the same.
14 . The method according to claim 9 , wherein a bottom width of each of the first recesses is different from a bottom width of each of the second recesses.
15 . A method for manufacturing a semiconductor structure, comprising: depositing a lower dielectric layer over a base structure, the lower dielectric layer including a first device region, a second device region spaced apart from the first device region, a first side region aside the first device region, and a second side region aside the second device region; forming a first gate element and a second gate element respectively in the first device region and the second device region; sequentially depositing a gate dielectric material layer and a channel material layer over the lower dielectric layer to cover the first gate element and the second gate element; removing portions of the channel material layer respectively on the first side region and the second side region, so as to form the channel material layer into a first channel layer on the first device region, and a second channel layer on the second device region; removing portions of the gate dielectric layer respectively on the first side region and the second side region, so as to form the gate dielectric layer into a first gate dielectric between the first channel layer and the first gate element, and a second gate dielectric between the second channel layer and the second gate element; depositing an upper dielectric layer to cover the first channel layer, the second channel layer, the first side region, and the second side region; forming grooves in the upper dielectric layer, the grooves partially exposing the second side region while the first channel layer and the second channel layer are prevented from being exposed from the grooves; after forming the grooves, performing a planarization process on the upper dielectric layer such that after the planarization process, a thickness of a first dielectric portion of the upper dielectric layer on the first channel layer is larger than a thickness of a second dielectric portion of the upper dielectric layer on the second channel layer; after the planarization process, forming first recesses in the first dielectric portion to partially expose the first channel layer, and forming second recesses in the second dielectric portion to partially expose the second channel layer; forming first source/drain contacts respectively in the first recesses, and forming second source/drain contacts respectively in the second recesses.
16 . The method according to claim 15 , wherein the first side region surrounds the first device region, and the second side region surrounds the second device region.
17 . The method according to claim 15 , wherein the first side region is not exposed from the grooves.
18 . The method according to claim 15 , wherein the grooves include at least one first groove which partially exposes the first side region, and second grooves which partially expose the second side region, a number of the at least one first groove being less than a number of the second grooves.
19 . The method according to claim 15 , wherein: the first recesses and the second recesses are formed simultaneously; and in forming the first recesses and the second recesses, portions of the upper dielectric layer, which cover the first side region and the second side region, are protected by a patterned protection layer.
20 . The method according to claim 19 , further comprising: removing the patterned protection layer after forming the first source/drain contacts and the second source/drain contacts.

Description

BACKGROUND At back end of line (BEOL) process, devices are incorporated into standard BEOL interconnecting structures. New methods are developed to make manufacturing of the BEOL devices easier and more effective. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 is a flow diagram illustrating a method for manufacturing a semiconductor structure in accordance with some embodiments. FIGS. 2 to 11 are schematic views illustrating intermediate stages of the method for manufacturing the semiconductor structure in accordance with some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “on,” “above,” “top,” “bottom,” “bottommost,” “upper,” “uppermost.” “lower,” “lowermost,” “over,” “beneath,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. For the purposes of this specification and appended claims, unless otherwise indicated, all numbers expressing amounts, sizes, dimensions, proportions, shapes, formulations, parameters, percentages, quantities, characteristics, or other numerical values used in the specification and claims, are to be understood as being modified in all instances by the term “about” even if the term “about” is not explicitly recited with the values, amounts or ranges. Accordingly, unless indicated to the contrary, the numerical parameters set forth in the following specification and appended claims are not and need not be exact, but may be approximations and/or larger or smaller than specified as desired, may encompass tolerances, conversion factors, rounding off, measurement error, and other factors known to those of skill in the art depending on the desired properties sought to be obtained by the presently disclosed subject matter. For example, the term “about,” when used with a value, can capture variations of, in some aspects ±10%, in some aspects ±5%, in some aspects ±2.5%, in some aspects ±1%, in some aspects ±0.5%, and in some aspects ±0.1% from the specified amount, as such variations are appropriate to perform the disclosed methods or employ the disclosed compositions. Back end of line (BEOL) may include a logic area and a memory area. The logic area may include vias or metal lines. The memory area may include devices, for example, but not limited to, memory devices, or other suitable devices. In some embodiments, the devices in the memory area may each include a channel, a gate, a dielectric disposed to isolate the channel from the gate, and source/drain contacts disposed on and connected to the channel opposite to the gate. A distance between two adjacent ones of the source/drain contacts is known as a channel length of the device. In some cases, in order to obtain a plurality of the devices having a uniform channel length, a self-aligned litho-etch-litho-etch (SALE-2) approach may be adopted in formation of the source/drain contacts. Specifically, formation of the source/drain contacts involves patterning of an interlayer dielectric disposed over the channels of the devices, so as to form source/drain recesses penetrating the interlayer dielectric. In patterning of the interlayer dielectric, spacers are formed to serve as patterning masks, such that any two adjacent ones of the source/drain