US-12622195-B2 - Methods for polishing bulk silicon devices

US12622195B2US 12622195 B2US12622195 B2US 12622195B2US-12622195-B2

Abstract

Methods for polishing bulk silicon are disclosed. In one aspect, mechanical polishing is facilitated by cyclically alternating between a silicon reactive slurry and deionized water while a mechanical polishing head operates on a surface. In exemplary aspects, the polishing head is polishing a bulk silicon carrier wafer to expose a backside of a radio frequency (RF) complementary metal oxide semiconductor (CMOS) switch, although other semiconductors may also benefit from exemplary aspects of the present disclosure. While the silicon slurry is present, a reaction between the bulk silicon and the slurry takes place allowing the polishing head to remove the bulk silicon. The deionized water interrupts this reaction and helps prevent overpolishing which might otherwise damage the device.

Inventors

Krishna Chetry
Ganesan Radhakrishnan

Assignees

QORVO US, INC.

Dates

Publication Date: 20260505
Application Date: 20230703

Claims (16)

1 . A method for exposing a semiconductor device for backside processing, the method comprising: providing the semiconductor device comprising a trench delimited by insulator sidewalls; grinding away a portion of a backside of the semiconductor device; selecting a slurry time based on a desired thickness of silicon to be removed from the backside of the semiconductor device, where the slurry time corresponds to an incubation period between a silicon slurry and silicon on the backside of the semiconductor device; polishing the backside of the semiconductor device with the silicon slurry and a polishing head such that silicon in the trench is removed at a pace faster than any silicon between the insulator sidewalls and the backside; and rinsing the semiconductor device with deionized water to remove the silicon slurry and interrupt the reaction between the silicon slurry and the silicon.
2 . The method of claim 1 , further comprising repeating the polishing and rinsing for multiple cycles.
3 . The method of claim 1 , wherein polishing the semiconductor device with the polishing head comprises rotating the polishing head.
4 . The method of claim 3 , wherein polishing the semiconductor device comprises rotating a polishing pad.
5 . The method of claim 1 , further comprising initially forming a structure of the semiconductor device in bulk silicon.
6 . The method of claim 5 , wherein polishing the semiconductor device removes a portion of the bulk silicon.
7 . The method of claim 5 , wherein forming the structure comprises forming a complementary metal oxide semiconductor.
8 . The method of claim 5 , wherein forming the structure comprises forming a radio frequency switch comprising a plurality of transistors.
9 . The method of claim 5 , further comprising adhering the structure to a carrier wafer.
10 . The method of claim 1 , further comprising opening a valve to apply the silicon slurry.
11 . The method of claim 1 , further comprising opening a valve to apply the deionized water.
12 . The method of claim 1 , further comprising timing the rinsing relative to the polishing a single atomic layer is removed.
13 . The method of claim 1 , wherein polishing comprises avoiding polishing the insulator sidewalls.
14 . The method of claim 1 , wherein a step height of removal approaches a steady state during polishing.
15 . The method of claim 1 , wherein the rate of removal during polishing approaches zero.
16 . A method for exposing a semiconductor device for backside processing, the method comprising: providing the semiconductor device comprising a trench delimited by insulator sidewalls; and polishing silicon out of the trench while avoiding polishing the insulator sidewalls by setting an incubation time for a silicon slurry used during polishing, such that when the silicon in the trench, a rate of removal approaches zero while a step height approaches a steady state value.

Description

PRIORITY APPLICATION This application claims the benefit of U.S. Provisional Patent Application Ser. No. 63/376,463, filed on Sep. 21, 2022, the disclosure of which is hereby incorporated herein by reference in its entirety. BACKGROUND I. Field of the Disclosure The technology of the disclosure relates generally to semiconductor manufacturing techniques and more particularly to polishing silicon wafers. II. Background Computing devices abound in modern society, and more particularly, mobile communication devices have become increasingly common. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from pure communication tools into sophisticated mobile entertainment centers, thus enabling enhanced user experiences. The evolution of computing devices is driven in large part by advances in the semiconductor technologies used to create integrated circuits capable of providing such functions. Commercial pressures to minimize power consumption, reduce size, reduce cost, or increase processing power continue to provide room for innovation in this space. SUMMARY Aspects disclosed in the detailed description include methods for polishing bulk silicon devices. In particular, mechanical polishing is facilitated by cyclically alternating between a silicon-reactive slurry and deionized water while a mechanical polishing head operates on a surface. In exemplary aspects, the polishing head is polishing a bulk silicon carrier wafer to expose a backside of a radio frequency (RF) complementary metal oxide semiconductor (CMOS) switch, although other semiconductors may also benefit from exemplary aspects of the present disclosure. While the silicon slurry is present, a reaction between the bulk silicon and the slurry takes place allowing the polishing head to remove the bulk silicon. The deionized water interrupts this reaction and helps prevent overpolishing of thin silicon layers (e.g., in trench areas) which might otherwise damage the device. In this regard in one aspect, a method for exposing a device for backside processing is disclosed. The method comprises polishing the device with a silicon slurry and a polishing head. The method also comprises rinsing the device with deionized water to remove the silicon slurry. In another aspect, a method for exposing a device for backside processing is disclosed. The method comprises polishing a backside of a device having a thin device layer by running a continuous cycle of reactive silicon slurry and deionized water. In another aspect, a mobile terminal comprising an integrated circuit comprising a device formed from the method for exposing a device for backside processing is disclosed. The method comprises polishing the device with a silicon slurry and a polishing head. The method also comprises rinsing the device with deionized water to remove the silicon slurry. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a cross-sectional elevation view of a semiconductor device; FIG. 1B is a top plan view of a semiconductor wafer subjected to traditional chemical mechanical polishing (CMP) steps; FIG. 1C is a top plan view of damaged doped silicon devices in the semiconductor wafer of FIG. 1B; FIG. 2 is a flowchart illustrating an exemplary process for polishing semiconductor wafers according to exemplary aspects of the present disclosure; FIGS. 3A-3D are cross-sectional elevation views showing the steps of the process of FIG. 2; FIG. 3E is a stylized representation of a polishing tool that may be used in the process of FIG. 2; FIG. 3F is a graph showing the cyclical process of alternating slurry and deionized water according to the process of FIG. 2; FIG. 3G is a time versus removal rate graph showing how incubation period varies by thickness of silicon along with a cross-sectional view of a wafer having different thicknesses corresponding to the curves on the graph; FIG. 4 is a graph showing the rate of removal compared to cycles juxtaposed with a height of a silicon material showing how interruption of the chemical reaction allows for a softer polishing of a semiconductor wafer; FIGS. 5A-5D show top planned views of a semiconductor wafer after various numbers of cycles of the present disclosure; and FIG. 6 is a block diagram of a mobile computing device which may include a semiconductor device made according to exemplary aspects of the present disclosure. DETAILED DESCRIPTION The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should