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US-12622204-B2 - Plasma etching chemistries of high aspect ratio features in dielectrics

US12622204B2US 12622204 B2US12622204 B2US 12622204B2US-12622204-B2

Abstract

A method for etching features in a stack below a patterned mask in an etch chamber is provided. The stack is cooled with a coolant with a coolant temperature below −20° C. An etch gas is flowed into the etch chamber. A plasma is generated from the etch gas. Features are selectively etched into the stack with respect to the patterned mask.

Inventors

  • Keren J. KANARIK
  • Samantha SiamHwa Tan
  • Yang Pan
  • Jeffrey Marks

Assignees

  • LAM RESEARCH CORPORATION

Dates

Publication Date
20260505
Application Date
20240202

Claims (20)

  1. 1 . A method for etching comprising: a) supporting a substrate on a chuck in a chamber of a plasma treatment system, the substrate including a silicon containing stack, and the chuck having a lower electrode; b) cooling the substrate to a temperature below −20° C.; c) providing a halogen containing gas; d) providing a phosphorus containing gas; and e) generating a plasma from the halogen containing gas and the phosphorus containing gas wherein the plasma modifies the silicon containing stack providing a modified layer; f) activating the modified layer of the stack; and g) etching features in the silicon containing stack.
  2. 2 . The method, as recited in claim 1 , further comprising providing a bias.
  3. 3 . The method, as recited in claim 1 , wherein the generating the plasma from the halogen containing gas and phosphorus containing gas into a plasma comprises providing RF power.
  4. 4 . The method, as recited in claim 1 , wherein the phosphorus containing gas comprises phosphorus pentafluoride (PF 5 ).
  5. 5 . The method, as recited in claim 1 , wherein the halogen containing gas comprises a free fluorine providing component.
  6. 6 . The method, as recited in claim 1 , further comprising providing one or more of a hydrogen containing component, a hydrocarbon containing component, a fluorocarbon containing component, and an iodine containing component.
  7. 7 . The method, as recited in claim 1 , further comprising providing oxygen gas.
  8. 8 . The method, as recited in claim 1 , further comprising providing a bias with a magnitude of at least 400 volts.
  9. 9 . The method, as recited in claim 1 , wherein the substrate comprises at least two different silicon containing layers.
  10. 10 . The method, as recited in claim 9 , wherein the at least two different silicon containing layers comprise a silicon oxide layer and a silicon nitride layer.
  11. 11 . The method, as recited in claim 9 , wherein the at least two different silicon containing layers comprise a silicon oxide layer and a polysilicon layer.
  12. 12 . A method for etching comprising: a) supporting a substrate on a chuck in a chamber of a plasma treatment system, the substrate including a silicon containing stack, and the chuck having a lower electrode; b) providing a halogen containing gas; c) providing a phosphorus containing gas; and f) providing RF power to generate a plasma from the halogen containing gas and the phosphorus containing gas wherein the plasma modifies the silicon containing stack providing a modified layer; g) activating the modified layer of the stack; and h) etching features in the silicon containing stack.
  13. 13 . The method, as recited in claim 12 , further comprising providing a bias.
  14. 14 . The method, as recited in claim 12 , wherein the phosphorus containing gas comprises phosphorus pentafluoride (PF 5 ).
  15. 15 . The method, as recited in claim 12 , further comprising cooling the substrate to a temperature below −20° C.
  16. 16 . The method, as recited in claim 12 , wherein the halogen containing gas comprises a free fluorine providing component.
  17. 17 . The method, as recited in claim 12 , further comprising providing one or more of a hydrogen containing component, a hydrocarbon containing component, a fluorocarbon containing component, and an iodine containing component.
  18. 18 . The method, as recited in claim 12 , further comprising providing oxygen gas.
  19. 19 . The method, as recited in claim 12 , further comprising providing a bias with a magnitude of at least 400 volts.
  20. 20 . The method, as recited in claim 12 , wherein the substrate comprises at least two different silicon containing layers.

Description

CROSS REFERENCE TO RELATED APPLICATION This application is a continuation of U.S. application Ser. No. 18/163,522 filed on Feb. 2, 2023, which is a continuation of U.S. application Ser. No. 16/979,372 filed on Sep. 9, 2020 (U.S. Pat. No. 11,594,429), which is a 371 of international Application No. PCT/US2019/021761 filed on Mar. 12, 2019, which claims the benefit of U.S. Provisional Application No. 62/644,095, filed on Mar. 16, 2018, which is incorporated herein by reference for all purposes. BACKGROUND The disclosure relates to a method of forming semiconductor devices on a semiconductor wafer. For example, in forming semiconductor devices, etch layers may be etched to form memory holes or lines or other semiconductor features. Some semiconductor devices may be formed by etching a single stack of silicon dioxide (SiO), for example, to form a capacitor in dynamic access random memory (DRAM). Other semiconductor devices may be formed by etching stacks of bilayers of alternating silicon dioxide (oxide) and silicon nitride (nitride) (ONON), or alternating silicon dioxide and polysilicon. Such stacks may be used in memory applications and three dimensional “not and” gates (3D NAND). The background description provided herein is for the purposes of generally presenting the context of the disclosure. These stacks tend to require relatively high aspect ratio (HAR) etching of the dielectrics. For high aspect ratio etches, examples of desired etch characteristics are high etch selectivity to the mask (such as an amorphous carbon mask), low sidewall etching with straight profiles, and high etch rate at the etch front. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure. SUMMARY To achieve the foregoing and in accordance with the purpose of the present disclosure, a method for etching features in a stack below a patterned mask in an etch chamber is provided. The stack is cooled with a coolant with a coolant temperature below −20° C. An etch gas is flowed into the etch chamber. A plasma is generated from the etch gas. Features are selectively etched into the stack with respect to the patterned mask. These and other features of the present disclosure will be described in more details below in the detailed description and in conjunction with the following figures. BRIEF DESCRIPTION OF THE DRAWINGS The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which: FIG. 1 is a high level flow chart of an embodiment. FIG. 2 is a schematic view of an etch chamber that may be used in an embodiment. FIG. 3 is a schematic view of a computer system that may be used in practicing an embodiment. FIGS. 4A-B are schematic cross-sectional views of a stack processed according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present disclosure will now be described in detail with reference to a few preferred embodiments thereof as illustrated in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art, that the present disclosure may be practiced without some or all of these specific details. In other instances, well known process steps and/or structures have not been described in detail in order to not unnecessarily obscure the present disclosure. FIG. 1 is a high level flow chart of an embodiment. In this embodiment, a stack is placed in an etch chamber (step 104). The stack is disposed below a patterned mask. The stack has at least one dielectric layer. The stack is cooled by a coolant with a coolant at a cryogenic temperature (step 108). An etch gas is provided by flowing the etch gas into the etch chamber (step 112). The etch gas is formed into an etch plasma (step 116). The stack is exposed to the plasma (step 120). A bias is provided to accelerate ions from the plasma to the stack (step 124). The stack is selectively etched with respect to the patterned mask by the etch plasma (step 128). The stack is removed from the etch chamber (step 132). Etching high aspect ratio structures is also commonly required through semiconductor materials such as silicon dioxide in order to produce semiconductor devices. Etching high aspect ratios requires a directional (anisotropic) etch, as distinct from an isotropic etch. Usually, directional etching is achieved by the use of ions in the plasma that are accelerated perpendicular to the wafer surface. For example, applying a bias of 10-5000 electron volts (eV) will accelerate the ions that exist in the plasma to the wafer surface. The i