US-12622220-B2 - Thermal pad for etch rate uniformity

US12622220B2US 12622220 B2US12622220 B2US 12622220B2US-12622220-B2

Abstract

Etch uniformity is improved by providing a thermal pad between an insert ring and electrostatic chuck in an etching chamber. The thermal pad provides a continuous passive heat path to dissipate heat from the insert ring and wafer edge to the electrostatic chuck. The thermal pad helps to keep the temperature of the various components in contact with or near the wafer at a more consistent temperature. Because temperature may affect etch rate, such as with etching hard masks over dummy gate formations, a more consistent etch rate is attained. The thermal pad also provides for etch rate uniformity across the whole wafer and not just at the edge. The thermal pad may be used in an etch process to perform gate replacement by removing hard mask layer(s) over a dummy gate electrode.

Inventors

Chin-huei Chiu
Tsung Fan Yin
Chen-Yi Liu
Hua-Li HUNG
Xi-Zong Chen
Yi-Wei Chiu

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Dates

Publication Date: 20260505
Application Date: 20210628

Claims (20)

1 . A device comprising: a wafer chuck; an outer ring having an outermost surface having an outer diameter and an inner surface having an inner diameter, wherein the inner surface of the outer ring mates with a surface of the wafer chuck; an insert ring, separate from the outer ring and having an outermost diameter that is less than the outer diameter of the outer ring, and laterally surrounding the wafer chuck, the insert ring having an edge portion which is over a portion of the wafer chuck; a collar ring on and covering the outer ring and at least partially covering the insert ring, wherein the collar ring has a lower surface with an extension that mates with a recess in an upper surface of the outer ring, wherein at least one of the outer ring, the insert ring, and the collar ring is a different material than others of the outer ring, the insert ring, and the collar ring; a first thermal pad disposed between the insert ring and the wafer chuck, an upper surface of the first thermal pad having a first interface with the insert ring and a lower surface of the first thermal pad having a second interface with the wafer chuck, the first thermal pad having a first innermost surface a first radial distance from a centermost point of the wafer chuck and a first outermost surface a second radial distance, greater than the first radial distance, from the centermost point of the wafer chuck, a second thermal pad disposed between the insert ring and the wafer chuck, an upper surface of the second thermal pad having a third interface with the insert ring and a lower surface of the second thermal pad having a fourth interface with the wafer chuck, the second thermal pad having a second innermost surface a third radial distance, greater than the second radial distance, from the centermost point of the wafer chuck and a second outermost surface a fourth radial distance, greater than the third radial distance from the centermost point of the wafer chuck; a first air-filled void between the first outermost surface of the first thermal pad and the second innermost surface of the second thermal pad; an adhesive layer, separate from the first thermal pad, providing adhesion between at least one of the first thermal pad and the second thermal pad and at least one of the insert ring and the wafer chuck; a cathode underlying and supporting the wafer chuck; an insulating ring underlying the outer ring, and surrounding the cathode, wherein the insulating ring has an inner surface contacting an outer surface of the cathode, and wherein the insulating ring has an upper surface including a projection, and the outer ring has a lower surface including a recess, and further wherein the projection of the insulating ring extends into and mates with the recess of the outer ring; a first platform support member surrounding the insulating ring and underlying the outer ring; and a second platform support member surrounding the first platform support member and extending between the first platform support member and the outer ring.
2 . The device of claim 1 , wherein the first thermal pad is inset into the insert ring.
3 . The device of claim 2 , wherein a bottom surface of the insert ring is level with the lower surface of the first thermal pad.
4 . The device of claim 1 , further comprising a second air-filled void between the first innermost surface of the first thermal pad and a sidewall of the wafer chuck, and a third air-filled void between the second outermost surface of the second thermal pad and a sidewall of the insert ring.
5 . The device of claim 1 , wherein the first air-filled void has a width, measured in the radial direction, of less than 40% of the width of the edge portion of the insert ring.
6 . The device of claim 1 , wherein the first thermal pad comprises a metallic material having a thermal conductivity greater than a thermal conductivity of the insert ring.
7 . The device of claim 1 , wherein a topmost surface of the insert ring is lower than a topmost surface of the outer ring.
8 . The device of claim 1 , wherein the wafer chuck has a first outermost diameter and the insert ring has a second outermost diameter that is equal to the first outermost diameter.
9 . An etching device comprising: an electrostatic chuck having a first portion wider than a second portion, the second portion being configured to support a wafer during an etching process; a shadow ring laterally surrounding the electrostatic chuck and vertically overlapping the first portion of the electrostatic chuck; an insert ring laterally surrounding the electrostatic chuck and vertically overlapping the first portion of the electrostatic chuck, the insert ring having an outermost diameter that is less than a diameter of an inner surface of the shadow ring, the insert ring forming an interface with the shadow ring, wherein the insert ring has a first thickness, measured from topmost surface to bottommost surface at a first point where the insert ring overlaps the shadow ring, has a second thickness less than the first thickness at a second point inside an innermost surface of the shadow ring, and has a third thickness less than the second thickness at an innermost surface of the insert ring; a collar ring on and covering the shadow ring and at least partially covering the insert ring, wherein the collar ring has a nominal bottommost surface and a projection extending from the nominal bottommost surface, the shadow ring has a nominal topmost surface and a recess extending into the nominal topmost surface, and wherein the projection extends into and mates with the recess, and further wherein at least one of the shadow ring, the insert ring, and the collar ring is a different material than others of the shadow ring, the insert ring, and the collar ring; one or more thermal pads interposed between the insert ring and the electrostatic chuck, the one or more thermal pads each having a first surface in contact with the insert ring and a second surface in contact with the electrostatic chuck, the one or more thermal pads each being configured to dissipate heat from the insert ring to the electrostatic chuck and being arranged as a series of concentric rings, the concentric rings of the one or more thermal pads being separated in the radial direction of the concentric rings, one from the other, by air-filled voids; a cathode underlying and supporting the wafer chuck; an insulating ring underlying the outer ring, and surrounding the cathode, wherein the insulating ring has an inner surface contacting an outer surface of the cathode, and wherein the insulating ring has an upper surface including a projection, and the outer ring has a lower surface including a recess, and further wherein the projection of the insulating ring extends into and mates with the recess of the outer ring; a first platform support member surrounding the insulating ring and underlying the outer ring; and a second platform support member surrounding the first platform support member and extending between the first platform support member and the outer ring.
10 . The etching device of claim 9 , wherein the insert ring includes a stepped portion in a bottom surface thereof, the one or more thermal pads being disposed in the stepped portion of the insert ring.
11 . The etching device of claim 9 , wherein: the shadow ring has a bottom step portion supporting the insert ring.
12 . The etching device of claim 9 , further comprising: a void disposed between a third surface of the one or more thermal pads and the electrostatic chuck or a void disposed between a fourth surface of the one or more thermal pads and the insert ring.
13 . The etching device of claim 9 , further comprising: at least two thermal pads; and a void disposed between the at least two thermal pads.
14 . The etching device of claim 13 , wherein the at least two thermal pads are disposed in a ringed configuration.
15 . The etching device of claim 9 , wherein the one or more thermal pads comprises a metallic filler material and has a thermal conductivity greater than a thermal conductivity of the insert ring.
16 . The etching device of claim 9 , wherein the one or more thermal pads have respective portions which are configured to overlap the second portion of the electrostatic chuck.
17 . The etching device of claim 9 , wherein the insert ring has a surface which is level with an upper surface of the electrostatic chuck.
18 . A device comprising: a thermal pad disposed on a lower ledge of a wafer chuck and adhered to the lower edge of the wafer chuck by an adhesive material separate from the thermal pad, the lower ledge surrounding a bottom portion of the wafer chuck; an insert ring disposed around the wafer chuck, the insert ring laterally surrounding the wafer chuck, the insert ring having a lower surface contacting an upper surface of the thermal pad, the insert ring having an upper surface level with an upper surface of the wafer chuck, wherein the upper surface of the insert ring has a first length in a direction parallel to a radius line of the wafer chuck and the lower surface of the insert ring has second length greater than the first length in the direction parallel to the radius line of the wafer chuck, wherein a lower surface and a first sidewall surface of the insert ring and an upper surface and a second sidewall surface of the wafer chuck define an enclosed cavity, and further wherein the thermal pad fills the enclosed cavity in a vertical direction while leaving one or more portions of the enclosed cavity in a horizontal direction unfilled by the thermal pad, the one more portions of the enclosed cavity in the horizontal direction being filled with air or helium, and further wherein the insert ring is detachably connected to the thermal pad; a shadow ring surrounding the insert ring and extending partially thereunder; and a collar ring overlying and covering the shadow ring and at least partially covering the insert ring, wherein at least one of the shadow ring, the insert ring, and the collar ring is a different material than others of the shadow ring, the insert ring, and the collar ring; a cathode underlying and supporting the wafer chuck; an insulating ring underlying the outer ring, and surrounding the cathode, wherein the insulating ring has an inner surface contacting an outer surface of the cathode, and wherein the insulating ring has an upper surface including a projection, and the outer ring has a lower surface including a recess, and further wherein the projection of the insulating ring extends into and mates with the recess of the outer ring; a first platform support member surrounding the insulating ring and underlying the outer ring; and a second platform support member surrounding the first platform support member and extending between the first platform support member and the outer ring.
19 . The device of claim 18 , wherein the thermal pad is inset into the insert ring, the insert ring having a bottommost surface lower than the upper surface of the thermal pad.
20 . The device of claim 18 , wherein the wafer chuck comprises heat dissipation features, the heat dissipation features configured to remove heat from the thermal pad.

Description

PRIORITY CLAIM AND CROSS-REFERENCE This application is a divisional of U.S. application Ser. No. 16/266,797, filed on Feb. 4, 2019, which is a continuation of U.S. application Ser. No. 15/726,103, filed on Oct. 5, 2017, now U.S. Pat. No. 10,199,252, issued on Feb. 5, 2019, which claims priority to and the benefit of U.S. Provisional Application No. 62/527,631, filed on Jun. 30, 2017, entitled “Thermal Pad for Etch Rate Uniformity,” which applications are hereby incorporated herein by reference. BACKGROUND With the increasing down-scaling of integrated circuits and the increasingly demanding requirements to the speed of integrated circuits, transistors need to have higher drive currents with increasingly smaller dimensions. Fin Field-Effect Transistors (FinFETs) were thus developed. The FinFETs include vertical semiconductor fins. The semiconductor fins are used to form source and drain regions, and to form channel regions between the source and drain regions. Shallow Trench Isolation (STI) regions are formed to define the semiconductor fins. The FinFETs also include gate stacks, which are formed on the sidewalls and the top surfaces of the semiconductor fins. In the replacement of dummy gates used in a gate-last fabrication, hard mask layer(s) of nitrides and/or oxides may be formed over a dummy gate electrode, such as polysilicon. Replacing the dummy gate can involve etching the hard masks, however, due to gate loading effects gate heights may have different heights and widths. Etching the hard masks may cause shortening of some of the gates, due in part to gate loading and etch rate variations in the etching chamber. In a plasma etching process, a gas is first introduced into a reaction chamber and then plasma is generated from the gas. This is accomplished by dissociation of the gas into ions, free radicals and electrons by using an RF (radio frequency) generator, which includes one or more electrodes. The electrons are accelerated in an electric field generated by the electrodes, and the energized electrons strike gas molecules to form additional ions, free radicals and electrons, which strike additional gas molecules, and the plasma eventually becomes self-sustaining. The ions, free radicals and electrons in the plasma react chemically with the layer material on the semiconductor wafer to form residual products which leave the wafer surface and, thus, etch the material from the wafer. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 illustrates an etching chamber, in accordance with some embodiments. FIG. 2 illustrates a platform of an etching chamber, in accordance with some embodiments. FIGS. 3-5 illustrate top down views of a cross-section of an etching platform, in accordance with various embodiments. FIGS. 6A-6B and 7A-7E illustrate a thermal pad configuration, in accordance with some embodiments. FIG. 8 is a flow diagram for providing a thermal pad, in accordance with some embodiments. FIGS. 9-19 illustrate various intermediate steps in the formation of a semiconductor device using a thermal pad, in accordance with some embodiments. FIGS. 20-26 illustrate various intermediate steps in the formation of a semiconductor device using a thermal pad, in accordance with some embodiments. FIGS. 27A and 27B illustrate topographical maps of a wafer etch rate using a thermal pad, in accordance with other embodiments. FIGS. 28A through 30B illustrate topographical maps of wafer gate heights and hard mask thicknesses at various stages of an etch process using a thermal pad, in accordance with some embodiments. FIG. 31 illustrates an example of a fin field-effect transistor (FinFET) in a three-dimensional view, in accordance with some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship b