US-12622228-B2 - Semiconductor device and a method for manufacturing a semiconductor device

US12622228B2US 12622228 B2US12622228 B2US 12622228B2US-12622228-B2

Abstract

A method of creating a vertical semiconductor device, the method includes the steps of performing a LOCal Oxidation of Silicon, LOCOS, process in a vertical trench of a semiconductor material so that oxide material is formed inside the vertical trench, and ledges are formed by the oxide material, inside the vertical trench, as a result of the LOCOS process, so that a lower region of reduced lateral distance is formed between the oxide material, at a base of the trench, depositing the trench with polysilicon and etching the polysilicon downward up to the oxide material using interferometric end point detection, so that polysilicon remains in the lower region.

Inventors

Steven PEAKE
MD Imran Siddiqui

Assignees

NEXPERIA B.V.

Dates

Publication Date: 20260505
Application Date: 20230509
Priority Date: 20220510

Claims (7)

1 . A method of creating a vertical semiconductor device, the method comprising the steps of: etching a vertical trench in a semiconductor material; depositing oxide at the bottom of the trench and forming an oxide layer at sidewalls of the trench; depositing nitride in the vertical trench; performing a LOCal Oxidation of Silicon (LOCOS) process in a vertical trench of a semiconductor material so that oxide material is formed inside the vertical trench, wherein the oxide material forms ledges, inside the vertical trench, as a result of the LOCOS process, so that a lower region of reduced lateral distance is formed between the oxide material, at a base of the trench and the ledges start at the end of the nitride, depositing the trench with polysilicon; and etching the polysilicon downward up to the oxide material using interferometric end point detection, so that polysilicon remains in the lower region, and subsequently, etching the polysilicon further downward for a predetermined time period after the oxide material is detected by the interferometric end point detection so that an etch depth is beyond the nitride.
2 . The method according to claim 1 , wherein the method comprises the additional steps of: growing a further oxide on top of the polysilicon in the vertical trench, and depositing a further polysilicon on the further oxide in the vertical trench.
3 . The method according to claim 1 , wherein the semiconductor material is of N-type.
4 . The method according to claim 1 , wherein the method further comprises the step of: etching a spacer by removing the nitride from above the deposited oxide at the bottom of the trench.
5 . The method according to claim 4 , further comprising the steps of: growing a further oxide on top of the polysilicon in the vertical trench, and depositing a further polysilicon on the further oxide in the vertical trench.
6 . The method according to claim 4 , wherein the semiconductor material is of N-type.
7 . The method according to claim 1 , wherein the predetermined time period is between 0.5-10 seconds.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit under 35 U.S.C. § 119(a) of European Application No. 22172478.4 filed May 10, 2022, the contents of which are incorporated by reference herein in their entirety. BACKGROUND 1. Field of the Disclosure The present disclosure generally relates to the field of semiconductor devices and, more specifically, to the field of manufacturing a semiconductor device having a vertical trench. 2. Description of the Related Art The present disclosure is directed to vertical discrete semiconductor devices. A vertical discrete semiconductor device is a device that has a vertical channel structure such that the current flows vertically from one side of the silicon wafer to the opposing second side of the wafer. One of such a semiconductor device is a (power) Metal Oxide Semiconductor, MOS, Field Effect Transistor, FET, typically comprises a source region towards a first major surface of the MOSFET and a drain region formed on a second major surface, opposite to the first major surface. A channel-accommodating region, i.e. a body region, is provided between the source and drain region, which channel-accommodating region is of a different conductivity type to that of the source and drain region. A conductive channel is to be provided between the source region and the drain region to assure that the MOSFET is turned on. To facilitate the creation of such a channel, a trench gate electrode is provided close to, but not in electrical contact with, the channel-accommodating region. Typical for the vertical structured MOSFET, or for any vertical semiconductor device, is that the current is conducted vertically from one surface to the other so as to achieve high drive capability. It may be realized by packing trenches on a chip, deep enough to cross the oppositely doped body region, i.e. channel-accommodating region, below the top surface. The design of power MOSFETs was made possible by the evolution of MOSFET and complementary metal-oxide-semiconductor, CMOS, technology which is used for manufacturing of integrated circuits. The power MOSFET has similar operating principle as a low-power counterpart, a lateral MOSFET. Lateral reduced surface field, RESURF, devices are also known in the art. The low on-resistance and the high breakdown voltage, BV, in lateral RESURF devices make them desirable for use in high voltage integrated circuit, HVIC, technologies. Although desirable, RESURF devices suffer from the unique requirement of accurate charge control and they are very sensitive to charge balance. Variations on charge control may lead to a lower BV causing limitations on the device performance. This control requirement complicates the manufacturability of RESURF devices. It is rather difficult to obtain a BV that is reproducible in fabrication. In recent years, RESURF technology has extended to low voltage, for example 25V to 150V POWERMOS applications. The industry preferred technique of achieving low voltage RESURF utilises a trench network with two polysilicon regions biased at gate and source potentials, respectively. This RESURF technology has matured greatly over the past decade and has become the industry's norm for achieving the required voltage rating, i.e. BVdss with very low specific Rdson's. What defines the voltage rating is the depth of the trench, particularly, the vertical length of the buried source polysilicon region. Essentially, you increase the depth of the trench and the vertical source polysilicon region to achieve a higher voltage rating. To define the buried source polysilicon region, you need to etch the trench, deposit the dielectric liner and then deposit the polysilicon. The deposited polysilicon is then plasma etched. The polysilicon region is etched to a depth defined by a timed etch. The dielectric oxide liner is then subsequentially etched with the polysilicon region acting as the mask for this etch. This process has a process control capability that results in an undesired variation of polysilicon and dielectric liner depth across a wafer. SUMMARY A summary of aspects of certain examples disclosed herein is set forth below. It should be understood that these aspects are presented merely to provide the reader with a brief summary of these certain embodiments and that these aspects are not intended to limit the scope of this disclosure. Indeed, this disclosure may encompass a variety of aspects and/or a combination of aspects that may not be set forth. It is an object of the present disclosure to provide for a method of creating a vertical semiconductor device. It is a further object of the present disclosure to provide for a semiconductor device obtained via the corresponding method. In a first aspect, there is provided a method of creating a vertical semiconductor device, the method comprising the steps of: performing a LOCal Oxidation of Silicon, LOCOS, process in a vertical trench of a semiconductor material such that oxid