US-12622229-B2 - Structure and method for test-point access in a semiconductor

Abstract

One example discloses a test-point access structure within a semiconductor, including: a target test-point configured to be coupled to a circuit within the semiconductor; a first doped region within the semiconductor configured to generate a first signal in response to an energy beam transmitted by a circuit editing (CE) tool; a second doped region within the semiconductor configured to generate a second signal in response to the energy beam transmitted by the CE tool; and a target pad coupling the target test-point to the first doped region; wherein the CE tool is configured to remove material from the semiconductor in response to the first signal and the second signal.

Inventors

• Kristofor Jason Dickson
• HUBERT MARTIN BODE
• Swaminathan Subramanian
• Kent Bradley Erington
• Kurt Ulrich Neugebauer
• William Franklin Johnstone

Assignees

• NXP USA, INC.

Dates

Publication Date

20260505

Application Date

20220803

Claims (19)

1. 1 . A test-point access structure within a semiconductor, the structure comprising: a target test-point configured to be coupled to a circuit within the semiconductor; a first doped region within the semiconductor configured to generate a first signal in response to an energy beam transmitted by a circuit editing (CE) tool; a second doped region within the semiconductor configured to generate a second signal in response to the energy beam transmitted by the CE tool; and a target pad coupling the target test-point to the first doped region; a void having an area defined by an amount of material removed by the CE tool in response to the first signal and the second signal; wherein the target test-point is coupled to a conducting net-wire within the circuit.
2. 2 . The structure of claim 1 : wherein the CE tool is a focused ion-beam (FIB) device; and wherein the first and second signals are generated in response to an ion energy beam emitted from the FIB device.
3. 3 . The structure of claim 1 : wherein a backside of the semiconductor is configured to receive the energy beam.
4. 4 . The structure of claim 1 : wherein the void includes a first area defined by when the CE tool stopped removing a first set of material in response to the first signal exceeding a threshold value; and wherein the first set of material has a first cross-sectional area.
5. 5 . The structure of claim 4 : wherein the void includes a second area defined by when the CE tool stopped removing a second set of material in response to the second signal exceeding a threshold value; and wherein the second set of material has a second cross-sectional area.
6. 6 . The structure of claim 5 : wherein the second cross-sectional area is smaller than the first cross-sectional area.
7. 7 . The structure of claim 1 : wherein the test-point access structure is placed in a spare tiling region of the semiconductor.
8. 8 . The structure of claim 1 : wherein the first doped region is a first Nwell structure; and wherein the circuit is not galvanically coupled to the first Nwell structure.
9. 9 . The structure of claim 8 : wherein the second doped region is a second Nwell structure; and wherein the second Nwell structure is galvanically coupled to the circuit.
10. 10 . The structure of claim 9 : wherein the first Nwell structure is configured to enable the first signal to be detected earlier than the second signal from the second Nwell structure.
11. 11 . The structure of claim 8 : wherein the first Nwell structure is a floating Nwell.
12. 12 . The structure of claim 1 : wherein the target pad is configured to be in temporary physical contact with a mechanical test-probe.
13. 13 . The structure of claim 1 : wherein the target pad is configured to be in temporary electrical contact with a mechanical test-probe; and wherein the test-probe is configured to measure an absolute voltage or current at the target test-point.
14. 14 . The structure of claim 1 : wherein the target pad is configured to be in temporary physical contact with a mechanical test-probe.
15. 15 . The structure of claim 1 : wherein the semiconductor includes a set of active tiles that are part of the circuit and a set of spare tiles that are unused by the circuit.
16. 16 . The structure of claim 15 : wherein the set of spare tiles are in the second set of material in the first doped region and are configured to be removed by the CE tool during milling.
17. 17 . The structure of claim 15 : wherein the set of active tiles are in the second doped region and are not removed by the CE tool during milling.
18. 18 . Method of enabling a circuit editing (CE) tool to physically probe a semiconductor using a test-point access structure: wherein the test-point access structure comprises, a target test-point configured to be coupled to a circuit within the semiconductor; a first doped region within the semiconductor; a second doped region within the semiconductor; a target pad coupling the target test-point to the first doped region; and wherein the method comprises, distributing a set of instructions, stored on a non-transitory, tangible computer readable storage medium, for configuring the circuit editing (CE) tool; wherein the instructions include, transmitting an energy beam from the circuit editing (CE) tool; measuring a first signal from the first doped region generated in response to the energy beam; measuring a second signal from the second doped region generated in response to the energy beam; and removing material from the semiconductor in response to the first signal and the second signal; wherein when the first signal exceeds a threshold value, then the CE tool is configured to stop removing a first set of material having a first cross-sectional area from the semiconductor; and wherein when the second signal exceeds a threshold value the CE tool is configured to stop removing a second set of material having a second cross-sectional area from the semiconductor.
19. 19 . A test-point access structure within a semiconductor, the structure comprising: a target test-point configured to be coupled to a circuit within the semiconductor; a first doped region within the semiconductor configured to generate a first signal in response to an energy beam transmitted by a circuit editing (CE) tool; a second doped region within the semiconductor configured to generate a second signal in response to the energy beam transmitted by the CE tool; and a target pad coupling the target test-point to the first doped region; a void having an area defined by an amount of material removed by the CE tool in response to the first signal and the second signal; wherein the test-point access structure is placed in a spare tiling region of the semiconductor.

Description

The present specification relates to systems, methods, apparatuses, devices, articles of manufacture and instructions for test-point access in a semiconductor. SUMMARY According to an example embodiment, a test-point access structure within a semiconductor, the structure comprising: a target test-point configured to be coupled to a circuit within the semiconductor; a first doped region within the semiconductor configured to generate a first signal in response to an energy beam transmitted by a circuit editing (CE) tool; a second doped region within the semiconductor configured to generate a second signal in response to the energy beam transmitted by the CE tool; and a target pad coupling the target test-point to the first doped region; wherein the CE tool is configured to remove material from the semiconductor in response to the first signal and the second signal. In another example embodiment, the CE tool is a focused ion-beam (FIB) device; and the first and second signals are generated in response to an ion energy beam emitted from the FIB device. In another example embodiment, the circuit editing (CE) tool transmits the energy beam to a backside of the semiconductor. In another example embodiment, when the first signal exceeds a threshold value, then the CE tool is configured to stop removing a first set of material having a first cross-sectional area from the semiconductor. In another example embodiment, when the second signal exceeds a threshold value the CE tool is configured to stop removing a second set of material having a second cross-sectional area from the semiconductor. In another example embodiment, the second cross-sectional area is smaller than the first cross-sectional area. In another example embodiment, the target test-point is coupled to a conducting net-wire within the circuit. In another example embodiment, the test-point access structure is placed in a spare tiling region of the semiconductor. In another example embodiment, the first doped region is a first Nwell structure; and the circuit is not galvanically coupled to the first Nwell structure. In another example embodiment, the second doped region is a second Nwell structure; and the second Nwell structure is galvanically coupled to the circuit. In another example embodiment, the first signal from the first Nwell structure is detected earlier than the second signal from the second Nwell structure. In another example embodiment, the first Nwell structure is a floating Nwell. In another example embodiment, the target pad is configured to be in temporary physical contact with a mechanical test-probe. In another example embodiment, the target pad is configured to be in temporary electrical contact with a mechanical test-probe; and the test-probe is configured to measure an absolute voltage or current at the target test-point. In another example embodiment, the target pad is configured to be in temporary physical contact with a mechanical test-probe. In another example embodiment, the semiconductor includes a set of active tiles that are part of the circuit and a set of spare tiles that are unused by the circuit. In another example embodiment, the set of spare tiles are in the second set of material in the first doped region and are configured to be removed by the CE tool during milling. In another example embodiment, the set of active tiles are in the second doped region and are not removed by the CE tool during milling. According to an example embodiment, a method of enabling a circuit editing (CE) tool to physically probe a semiconductor using a test-point access structure: wherein the test-point access structure comprises, a target test-point configured to be coupled to a circuit within the semiconductor; a first doped region within the semiconductor; a second doped region within the semiconductor; a target pad coupling the target test-point to the first doped region; and wherein the method comprises, distributing a set of instructions, stored on a non-transitory, tangible computer readable storage medium, for configuring the circuit editing (CE) tool; wherein the instructions include, transmitting an energy beam from the circuit editing (CE) tool; measuring a first signal from the first doped region generated in response to the energy beam; measuring a second signal from the second doped region generated in response to the energy beam; and removing material from the semiconductor in response to the first signal and the second signal. The above discussion is not intended to represent every example embodiment or every implementation within the scope of the current or future Claim sets. The Figures and Detailed Description that follow also exemplify various example embodiments. Various example embodiments may be more completely understood in consideration of the following Detailed Description in connection with the accompanying Drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 represents an example plan view of a test-point access st