US-12622230-B2 - Test structure and method for forming the same, and semiconductor memory

US12622230B2US 12622230 B2US12622230 B2US 12622230B2US-12622230-B2

Abstract

A test structure includes a plurality of word lines and a plurality of bit lines. A vertical gate-all-around (VGAA) transistor is formed at the intersection of each word line and each bit line. The test structure includes a first area and a second area. The second area is arranged outside the first area, the word lines in the first area and the word lines in the second area are disconnected, and the bit lines in the first area and the bit lines in the second area are disconnected. The plurality of VGAA transistors located in the first area form a test array, and a VGAA transistor located in the middle of the test array is a device to be tested.

Inventors

Yi Jiang
Deyuan Xiao
Qinghua HAN
Meng-Feng Tsai

Assignees

CHANGXIN MEMORY TECHNOLOGIES, INC.

Dates

Publication Date: 20260505
Application Date: 20220926
Priority Date: 20220623

Claims (5)

1 . A test structure, comprising a plurality of word lines and a plurality of bit lines, wherein a vertical gate-all-around (VGAA) transistor is formed at an intersection of each word line and each bit line; the test structure comprises a first area and a second area, wherein the second area is arranged outside the first area, word lines in the first area and word lines in the second area are disconnected, and bit lines in the first area and bit lines in the second area are disconnected; and a plurality of VGAA transistors located in the first area form a test array, and a VGAA transistor located in the middle of the test array is a device to be tested; a gate contact node and a source contact node; wherein the gate contact node is located in the first area, and the gate contact node is connected with a control end of the device to be tested through a word line; and the source contact node is located in the first area, and the source contact node is connected with a first end of the device to be tested through a bit line; a first metal layer, a second metal layer, and a third metal layer; wherein the first metal layer covers and is connected with the gate contact node, and the first metal layer extends to an outside of the second area; the second metal layer covers and is connected with the source contact node, and the second metal layer extends to the another outside of the second area; the third metal layer covers and is connected with a second end of the device to be tested, and the third metal layer extends to the outside of the second area; wherein extension directions of the first metal layer, the second metal layer, and the third metal layer to the second area are different, and the first metal layer, the second metal layer and the third metal layer do not intersect with each other.
2 . The test structure of claim 1 , wherein the first metal layer is configured to connect a gate of the device to be tested, the second metal layer is configured to connect a source of the device to be tested, and the third metal layer is configured to connect a drain of the device to be tested.
3 . The test structure of claim 1 , wherein a width of the first metal layer in a bit line direction covers three word lines, and the first metal layer does not cover the test array; and a width of the second metal layer in a word line direction covers three bit lines, and the second metal layer does not cover the test array.
4 . The test structure of claim 1 , wherein a size of the test array is an (m×n) array, where m and n are both positive integers, and m and n are equal or unequal; wherein values of m and n include at least any one of the following: 3, 4, 5, 9, or 16.
5 . A semiconductor memory, comprising the test structure of claim 1 .

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This is a continuation of International Patent Application No. PCT/CN2022/109733 filed on Aug. 2, 2022, which claims priority to Chinese Patent Application No. 202210844886.2 filed on Jun. 23, 2022. The disclosures of the above-referenced applications are hereby incorporated by reference in their entirety. BACKGROUND A Vertical gate-all-around (VGAA) transistor has more advantages in the aspects of scalability, high performance and low power consumption and is considered as the key core technology of a next-generation integrated circuit. However, the performance of the VGAA transistor is more affected by the resistance of bit line and word line. Therefore, when the VGAA transistor is tested, it is necessary to eliminate the influence of the resistance of bit line and the word line as much as possible, and to focus well on the performance of the VGAA transistor itself. SUMMARY The present disclosure relates to, but is not limited to, a test structure and a method for forming the same, and a semiconductor memory. The technical solutions of the present disclosure are implemented as follows. In a first aspect, embodiments of the present disclosure provide a test structure. The test structure may include a plurality of word lines and a plurality of bit lines. A VGAA transistor is formed at an intersection of each word line and each bit line. The test structure may include a first area and a second area. The second area is arranged outside the first area, the word lines in the first area and the word lines in the second area are disconnected, and the bit lines in the first area and the bit lines in the second area are disconnected. The plurality of VGAA transistors located in the first area together form a test array, and a VGAA transistor located in the middle of the test array is a device to be tested. In a second aspect, the embodiments of the present disclosure provide a method for forming a test structure. The method may include the following operations. A test structure is provided, and the test structure is patterned to form a first area and a second area. Herein, the test structure may include a plurality of word lines and a plurality of bit lines, and a VGAA transistor is formed at the intersection of each word line and each bit line. The word lines in the first area and the word lines in the second area are disconnected, and the bit lines in the first area and the bit lines in the second area are disconnected. A test array is formed using a plurality of VGAA transistors located in the first area, and a VGAA transistor located in the middle of the test array is a device to be tested. In a third aspect, the embodiments of the present disclosure provide a semiconductor memory, which may include the test structure as described in the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a schematic diagram of a partial three-dimensional structure of a VGAA transistor. FIG. 1B is a cross-sectional view of a VGAA transistor in a word line direction. FIG. 1C is a cross-sectional view of a VGAA transistor in a bit line direction. FIG. 2 is a schematic diagram of a test structure. FIG. 3 is a schematic diagram of an abnormal test result of a VGAA transistor. FIG. 4 is a schematic diagram of a test structure according to embodiments of the present disclosure. FIG. 5 is a schematic diagram of another test structure according to embodiments of the present disclosure. FIG. 6 is a schematic diagram of a method for forming a test structure according to embodiments of the present disclosure. FIG. 7A is a first schematic diagram of a process of forming a test structure according to embodiments of the present disclosure. FIG. 7B is a second schematic diagram of a process of forming a test structure according to embodiments of the present disclosure. FIG. 7C is a third schematic diagram of a process of forming a test structure according to embodiments of the present disclosure. FIG. 7D is a fourth schematic diagram of a process of forming a test structure according to embodiments of the present disclosure. FIG. 7E is a fifth schematic diagram of a process of forming a test structure according to embodiments of the present disclosure. FIG. 7F is a sixth schematic diagram of a process of forming a test structure according to embodiments of the present disclosure. FIG. 7G is a seventh schematic diagram of a process of forming a test structure according to embodiments of the present disclosure. FIG. 8 is an eighth schematic structural diagram of compositions of a semiconductor memory according to embodiments of the present disclosure. DETAILED DESCRIPTION The technical solutions in embodiments of the present disclosure will be clearly and completely described in conjunction with the drawings in the embodiments of the present disclosure. It should be understood that the specific embodiments described herein are only used to illustrate the related application, but are not intended to